Datasheet

22 Intel
®
Xeon
®
Processor E7-8800/4800/2800 Product Families
September 2012 Specification Update
rollover. When generated, the error signal is sent to the system configuration controller
where it is processed into a system management interrupt (SMI).
Under specific conditions, a RAS recoverable error signal is generated and logged in a
physical layer port, but the interrupt is not generated. More specifically, the error signal
is lost on the way from the port to the system configuration controller.
The problem arises when the error signal passes through a port that has been disabled.
Each physical layer port has its own internal clock generator. When a port is disabled,
its clock generator is off, and the error signal cannot propagate through that port.
Implication: If any physical layer ports are configured to signal errors of the RAS recoverable type,
then depending on the pattern of disabled ports, the errors may be logged properly in
the physical layer port, but a matching system management interrupt may not occur.
Fatal error signals are not affected; they will always be transmitted successfully.
Workaround: Do not disable physical layer ports, or if they have been disabled then re-enable them,
such that ports that may generate RAS recoverable errors have paths to send their
error signals to the system configuration controller.
Status: For the steppings affected, see the Summary Tables of Changes.
BP23. Executing The WAKEUP Leaf of The GETSEC Instruction Multiple Times
May Lead to a Machine Check Error
Problem: The GETSEC WAKEUP leaf broadcasts a wakeup message to all logical processors
currently in a SENTER sleep state. It is sufficient to execute this instruction leaf once,
per MLE (Measured Launch Event) launch, by the ILP (Initiating Logical Processor).
Executing the leaf multiple times may lead to buffer entry corruptions resulting in
machine check errors.
Implication: MLE launch may hang when GETSEC WAKEUP leaf is executed multiple times during the
same launch.
Workaround: MLE launch software can workaround this erratum by avoiding multiple GETSEC
WAKEUP leaf instruction executions.
Status: For the steppings affected, see the Summary Tables of Changes.
BP24. CKE-Lo Feature Can Not be Disabled When Memory Controller
Transactions are Active
Problem: If the CKE-Lo (Clock Enable de-asserted) feature is disabled when the memory
controller transactions are active, then it may cause the system to hang.
Implication: Disabling the CKE-Lo feature when the memory controller transactions are active, may
result in the transactions timing out causing the system to hang.
Workaround: Software is required to quiesce memory traffic (including patrol scrub) before disabling
the CKE-Lo feature.
Status: For the steppings affected, see the Summary Tables of Changes.
BP25. Executing The Intel TXT GETSEC SENTER Instruction Leaf May Lead to
a Machine Check Error
Problem: The GETSEC SENTER instruction leaf broadcasts a message in order to handshake/
rendezvous between different logical processors. The processor uses incorrect byte-
enables when broadcasting this message to remote processor sockets. This may result
in a Machine Check error on multisocket platforms.
Implication: Due to this erratum, Intel TXT AC Modules cannot be run on multisocket platforms.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.