Datasheet
Intel
®
Xeon
®
Processor E7-8800/4800/2800 Product Families 19
Specification Update September 2012
BP9. Memory Controller Patrol Scrub Ceases to Function with CRC Errors
and the IMT31 Reclaim Feature Enabled
Problem: The processor does not fully implement the protocol in the Memory Controller-Home
Agent for sharing the IMT31 (In-flight Memory Table) entry resulting in a patrol scrub
deadlock. This issue can occur whenever the Error Flow State is invoked in response to
CRC errors or hardware injected periodic ZQCAL (ZQ Calibration).
Implication: Patrol scrub may not function with CRC errors and the IMT31 reclaim feature enabled.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BP10. Electrically Idle Intel
®
SMI and Intel
®
QPI Lanes May Deliver Data
that May Look Like Deskew Headers
Problem: Intel
®
SMI or Intel
®
QPI lanes that are not physically connected on the board, or have
become unconnected, may result in a deskew failure. A deskew failure or
environmental issue may lead to Intel
®
SMI link transitioning into a Lane Failover
Mode.
Implication: Improper deskew headers may be observed if the Intel
®
SMI lane of a port is not
physically connected. The Intel
®
SMI link may transition into Lane Fail-over mode.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BP11. A Sequence of Instruction Fetches and Snoops to Locked Cache Lines
May Cause Processor to Hang
Problem: During a sequence of instruction fetches with specific address relationships to other
system traffic a snoop beat pattern that includes snoops to locked cache lines may
become established which could cause the processor to hang.
Implication: The processor may hang under a set of conditions involving instruction fetches, and
snoops to locked cache lines.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
BP12. Writing to Unimplemented Bits of UU_CR_U_MSR_PMON_EVNT_SEL
MSR does Not Result in #GP Fault
Problem: The bits [31:23,17,15:8] in UU_CR_U_MSR_PMON_EVNT_SEL MSR (C10H) are not
implemented on the processor and are marked as reserved. Due to this erratum writing
1's to these bits does not generate a #GP (General Protection Fault) as expected.
Implication: Writing 1's to the unimplemented bits in UU_CR_U_MSR_PMON_EVNT_SEL MSR does
not result in a #GP fault.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BP13. Mixed Rank Size Memory Configurations May Cause a Missing Refresh
Event
Problem: When using DIMMs of different rank sizes on the same memory channel, a refresh may
be missed when a write command to a memory rank is blocked by sustained reads to
another memory rank. This erratum has been seen only in a synthetic testing
environment. Intel has not observed this erratum with any commercially available
software.
Implication: A missing refresh may cause the refresh rate to be lower than the programmed value.