Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 99
Interfaces
2.3.9.1 SMBus Configuration and Memory Block-Size Reads
Figure 31. SMBus Block-Size Configuration Register Read
Figure 32. SMBus Block-size Memory Register Read
S 1110_1X0 W A Cmd = 11010010 A Byte cnt = 4 A Bus Num A Dev / Func A
Rsv[3:0] & Addr[11:8] A Regoff [7:0] A PEC A P
Write address
for a Read
sequence
S 1110_1X0 W A Cmd = 11010010 A
Sr
1110_1X0 R A Byte cnt = 5 A Status A Data [31:24] A Data [23:16] A
Data [15:8] A Data [7:0] A PEC N P
Read data
sequence
Poll until
Status[7] = 0
S 1110_1X0 W A Cmd = 11110010 A Byte cnt = 4 A MemRegion A Addr off[23:16] A
Addr off[15:8] A Addr off[7:0] A PEC A P
Write address
for a Read
sequence
S 1110_1X0 W A Cmd = 11110010 A
Sr
1110_1X0 R A Byte cnt = 5 A Status A Data [31:24] A Data [23:16] A
Data [15:8] A Data [7:0] A PEC N P
Read data
sequence
Poll until
Status[7] = 0