Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 97
Interfaces
2.3.6 SMBus Initiated Southbound Configuration Cycles
The platform SMBus master agent that is connected to an IIO slave SMBus agent can
request a configuration transaction to a downstream PCI-Express device. If the address
decoder determines that the request is not intended for this IIO (i.e. not the IIO’s bus
number), it sends the request to port with the bus address. All requests outside ofthis
range are sent to the legacy ESI port for a master abort condition.
2.3.7 SMBus Error Handling
SMBus Error Handling feature list:
• Errors are reported in the status byte field.
• Errors in Table 53 are also collected in the FERR and NERR registers.
The SMBus slave interface handles two types of errors: internal and PEC. For example,
internal errors can occur when the IIO issues a configuration read on the PCI-Express
port and that read terminates in error. These errors manifest as a Not-Acknowledge
(NACK) for the read command (End bit is set). If an internal error occurs during a
configuration write, the final write command receives a NACK just before the stop bit. If
the master receives a NACK, the entire configuration transaction should be
reattempted.
If the master supports packet error checking (PEC) and the PEC_en bit in the command
is set, then the PEC byte is checked in the slave interface. If the check indicates a
failure, then the slave will NACK the PEC packet.
Each error bit must be routed to the FERR and NERR registers for error reporting. The
status field encoding is defined in Table 53. This field reports if an error occurred. If
bits[2:0] are 000b then transaction was successful only to the extent that the IIO is
aware. In other words a successful indication here does not necessarily mean that the
transaction was completed correctly for all components in the system.
The busy bit is set whenever a transaction is accepted by the slave. This is true for
reads and writes but the affects may not be observable for writes. This means that
since the writes are posted and the communication link is so slow the master should
never see a busy condition. A time-out is associated with the transaction in progress.
When the time-out expires a time-out error status is asserted.
2.3.8 SMBus Interface Reset
The slave interface state machine can be reset in several ways. The first two items are
defined in the SMBus rev2.0 specification.
• The master holds SCL low for 25 ms cumulative. Cumulative in this case means
that all the “low time” for SCL is counted between the Start and Stop bit. If this
totals 25 ms before reaching the Stop bit, the interface is reset.
Table 53. Status Field Encoding for SMBus Reads
Bit Description
7Busy
6:3 Reserved
2:0
100-111: Reserved
011: Master Abort. An error that is reported by the IIO with respect to this transaction.
010: Completer Abort. An error is reported by downstream PCI Express device with respect
to this transaction.
001: Memory Region encoding error. This bit is set if a memory region is not valid.
000: Successful