Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
96 Order Number: 323103-001
If the Mem/Cfg (MemTrans) bit as described in Table 49, “SMBus Command Encoding”
is cleared then the address field represents the standard PCI register addressing
nomenclature namely; bus, device, function and offset.
If the Mem/Cfg bit is set, the address field has a new meaning. Bits [23:0] hold a linear
memory address and bits[31:24] is a byte to indicate which memory region it is.
Table 52 describes the selections available. A logic one in a bit position enables that
memory region to be accessed. If the destination memory byte is zero then no action is
taken (no request is sent to the configuration master).
If a memory region address field is set to a reserved space the IIO slave will perform
the following:
The transaction is not executed.
The slave releases the SCL (Serial Clock) signal.
The master abort error status is set.
[4] 0
[3] 1
[2] Inversion of DMI_PE_CFG# strap pin
[1] 0
[0]
Read/Write# bit. This bit is in the slave address field to indicate a read or
write operation. It is not part of the SMBus slave address.
Table 51. SMBus Slave Address Format
Slave Address Field Bit Position Slave Address Source
Table 52. Memory Region Address Field
Bit Field Memory Region Address Field
0Fh LT_QPII/LT_LT BAR
0Eh LT_PR_BAR
0Dh LT_PB_BAR
0Ch NTB Secondary memory BAR, (SBAR01BASE)
0Bh NTB Primary memory BAR, (PBAR01BASE)
0Ah DMI RC memory BAR, (DMIRCBAR)
09h IOAPIC memory BAR, (MBAR/ABAR)
08h Intel
®
VT-d memory BAR, (VTBAR)
07h Intel
®
QuickData Technology memory BAR 7,(CB_BAR7)
06h Intel
®
QuickData Technology memory BAR 6,(CB_BAR6)
05h Intel
®
QuickData Technology memory BAR 5,(CB_BAR5)
04h Intel
®
QuickData Technology memory BAR 4,(CB_BAR4)
03h Intel
®
QuickData Technology memory BAR 3,(CB_BAR3)
02h Intel
®
QuickData Technology memory BAR 2,(CB_BAR2)
01h Intel
®
QuickData Technology memory BAR 1,(CB_BAR1)
00h Intel
®
QuickData Technology memory BAR 0 (CB_BAR0)