Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 93
Interfaces
function) space or in memory mapped space. The PECI registers are not within the
IIO portion of the processor, and therefore cannot be accessed from the SMBus.
— In a dual processor configuration, the SMBus Master (BMC for example) must
use the SMBus slave local to each processor to access the IIO registers in that
processor as remote peer to peer IO and configuration cycles are not
supported.
• The SMBus interface acts as a side-band configuration access and must service all
SMBus config transactions even in the presence of a processor deadlock condition.
• The slave SMBus supports Packet Error Checking (can be disabled) as defined in
the SMBus 2.0 specification.
• The SMBus requires the SMBus master to poll the busy bit to determine if the
previous transaction has completed. For reads, this is after the repeated start
sequence.
2.3.2 Master SMBus
The IIO also includes a SMBUS master for PCIe hot plug. See Section 11.7.2, “PCIe Hot
Plug” for further information.
2.3.3 SMBus Physical Layer
The component fabrication process does not support the pull-up voltage required by
the SMBus protocol. Therefore, it will be required that voltage translators be placed on
the platform to accommodate the differences in driving voltages. The IIO SMBus pads
will operate at voltage of 1.1v. The IIO complies with the SMBus SCL frequency of
100 kHz.
2.3.4 SMBus Supported Transactions
The IIO supports six SMBus commands associated in read/write groups with three data
sizes. Read transactions require two SMBus sequences: writing requested read address
to internal register stack and the read command to extract data once it is available.
Write transactions are a single sequence containing both address and data.
Supported transactions:
To support longer PCIe time-outs the SMBus master is required to poll the busy bit to
know when data in the stack contains the desired data. This applies to both reads and
writes. The protocol diagrams (Figure 31 through Figure 37) only show the polling in
read transactions. This is due to the length of PCIe time-outs, which may be as long as
several seconds. This will violate the SMBus spec of a maximum of 25 ms. To overcome
this limitation, the SMBus slave will request the config master for access, once granted
the slave asserts its busy bit and releases the link. The SMBus master is free to address
other devices on the link or poll the busy bit until the IIO has completed the
transaction.
Sequencing these commands initiates internal accesses to the component’s
configuration registers. For high reliability, the interface supports the optional Packet
Error Checking feature (CRC-8) and is enabled or disabled with each transaction.
• Block Write (Dword sized data packet) • Word Read (Word sized data packet)
• Block Read (Dword sized data packet) • Byte Write (Byte sized data packet)
• Word Write (Word sized data packet) • Byte Read (Byte sized data packet)