Datasheet
Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
92 Order Number: 323103-001
2.2.7.6 Processor Reset
The Intel
®
Xeon
®
processor C5500/C3500 series PECI client is fully reset on all
RSTIN# assertions. Upon deassertion of RSTIN#, where power is maintained to the
processor (otherwise known as a ‘warm reset’), the following are true:
• The PECI client assumes a bus Idle state.
• The Thermal Filtering Constant is retained.
• PECI Node ID is retained.
• GetTemp() reading resets to 0x0000.
• Any transaction in progress is aborted by the client (as measured by the client no
longer participating in the response).
• The processor client is otherwise reset to a default configuration.
2.3 SMBus
The Intel
®
Xeon
®
processor C5500/C3500 series has two V2.0 SMBus interfaces, one
slave and one master. A third V2.0 SMBus master is provided by the PCH. The slave
interface is a two signal/pin interface supporting a clock and a data line. The master
interface is a two signal/pin interface supporting a clock, and a data line.
2.3.1 Slave SMBus
The IIO includes an SMBus Specification, Revision 2.0 compliant slave port. This SMBus
slave port provides server management (SM) visibility into all configuration registers in
the IIO. The IIO’s SMBus interface is capable of both accessing IIO registers and
generating in-band downstream configuration cycles to other components.
SMBus operations may be split into two upper level protocols: writing information to
configuration registers and reading configuration registers. This section describes the
required protocol for an SMBus master to access the IIO’s internal configuration
registers. See the SMBus Specification, Revision 2.0 for the specific bus protocol,
timings, and waveforms.
Warning: Since the IIO clock frequency is changed during the boot sequence, access to/from the
IIO through the SMbus is not permitted during boot up.
SMBus features:
• The SMBus allows access to any register within the IIO portion of the Intel
®
Xeon
®
processor C5500/C3500 series, whether the CSR exists in PCI (bus, device,
Table 48. PECI Client Response During S1
Command Response
Ping() Fully functional
GetDIB() Fully functional
GetTemp() Fully functional
PCIConfigRd() Fully functional
PCIConfigWr() Fully functional
MbxSend() Fully functional
MbxGet() Fully functional