Datasheet
Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
90 Order Number: 323103-001
2.2.7 Client Management
2.2.7.1 Power-up Sequencing
The PECI client is fully reset during processor RSTIN# assertion. This means that any
transactions on the bus will be completely ignored, and the host will read the response
from the client as all zeroes. After processor RSTIN# deassertion, the Intel
®
Xeon
®
processor C5500/C3500 series PECI client is operational enough to participate in timing
negotiations and respond with reasonable data. However, the client data is not
guaranteed to be fully populated until greater than 500 µS after processor RSTIN# is
deasserted. Until that time, data may not be ready for all commands. The client
responses to each command are as follows:
If the processor is tri-stated using power-on-configuration controls, the PECI client will
also be tri-stated.
Table 45. Error Codes and Descriptions
Error Code Description
0x8000 General Sensor Error (GSE)
Table 46. PECI Client Response During Power-Up (During ‘Data Not Ready’)
Command Response
Ping() Fully functional
GetDIB() Fully functional
GetTemp() Client responds with a ‘hot’ reading, or 0x0000
PCIConfigRd() Fully functional
PCIConfigWr() Fully functional
MbxSend() Fully functional
MbxGet() Client responds with Abort FCS (if MbxSend() has been previously issued)
Figure 30. PECI Power-up Timeline
Bclk
Vtt
VttPwrGd
SupplyVcc
VccPwrGd
RSTIN#
Mclk
Intel® QPI pins
uOp execution
CSI training idle running
Reset uCode Boot BIOS
PECI Client Status
In Reset Data Not Rdy Fully Operational
PECI Node ID
x
0b1 or 0b0