Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 9
3.19.4.7 CORERRMSK: Correctable Error Mask ...................................... 210
3.19.4.8 ERRCAP: Advanced Error Capabilities and Control Register ......... 211
3.19.4.9 HDRLOG: Header Log............................................................ 211
3.19.4.10 RPERRCMD: Root Port Error Command Register ........................ 212
3.19.4.11 RPERRSTS: Root Port Error Status Register .............................. 212
3.19.4.12 ERRSID: Error Source Identification Register ............................ 214
3.19.4.13 SSMSK: Stop and Scream Mask Register.................................. 214
3.19.4.14 APICBASE: APIC Base Register ............................................... 215
3.19.4.15 APICLIMIT: APIC Limit Register............................................... 215
3.19.4.16 ACSCAPHDR: Access Control Services Extended Capability
Header.................................................................................. 215
3.19.4.17 ACSCAP: Access Control Services Capability Register ................. 215
3.19.4.18 ACSCTRL: Access Control Services Control Register................... 216
3.19.4.19 PERFCTRLSTS: Performance Control and Status Register............ 216
3.19.4.20 MISCCTRLSTS: Misc. Control and Status Register...................... 216
3.19.4.21 PCIE_IOU0_BIF_CTRL: PCIE IOU0 Bifurcation Control Register.... 217
3.19.4.22 NTBDEVCAP: PCI Express Device Capabilities Register ............... 217
3.19.4.23 LNKCAP: PCI Express Link Capabilities Register......................... 219
3.19.4.24 LNKCON: PCI Express Link Control Register.............................. 221
3.19.4.25 LNKSTS: PCI Express Link Status Register................................ 223
3.19.4.26 SLTCAP: PCI Express Slot Capabilities Register ......................... 225
3.19.4.27 SLTCON: PCI Express Slot Control Register............................... 227
3.19.4.28 SLTSTS: PCI Express Slot Status Register ................................ 229
3.19.4.29 ROOTCON: PCI Express Root Control Register........................... 231
3.19.4.30 DEVCAP2: PCI Express Device Capabilities 2 Register ................ 233
3.19.4.31 DEVCTRL2: PCI Express Device Control 2 Register..................... 234
3.19.4.32 LNKCON2: PCI Express Link Control Register 2 ......................... 235
3.19.4.33 LNKSTS2: PCI Express Link Status 2 Register ........................... 236
3.19.4.34 CTOCTRL: Completion Time-out Control Register....................... 236
3.19.4.35 PCIE_LER_SS_CTRLSTS: PCI Express Live Error Recovery/Stop
and Scream Control and Status Register .................................... 236
3.19.4.36 XPCORERRSTS - XP Correctable Error Status Register................ 236
3.19.4.37 XPCORERRMSK - XP Correctable Error Mask Register ................. 236
3.19.4.38 XPUNCERRSTS - XP Uncorrectable Error Status Register............. 236
3.19.4.39 XPUNCERRMSK - XP Uncorrectable Error Mask Register.............. 236
3.19.4.40 XPUNCERRSEV - XP Uncorrectable Error Severity Register.......... 237
3.19.4.41 XPUNCERRPTR - XP Uncorrectable Error Pointer Register............ 237
3.19.4.42 UNCEDMASK: Uncorrectable Error Detect Status Mask ............... 237
3.19.4.43 COREDMASK: Correctable Error Detect Status Mask .................. 237
3.19.4.44 RPEDMASK - Root Port Error Detect Status Mask....................... 237
3.19.4.45 XPUNCEDMASK - XP Uncorrectable Error Detect Mask Register.... 237
3.19.4.46 XPCOREDMASK - XP Correctable Error Detect Mask Register ....... 237
3.19.4.47 XPGLBERRSTS - XP Global Error Status Register........................ 237
3.19.4.48 XPGLBERRPTR - XP Global Error Pointer Register....................... 237
3.20 PCI Express Configuration Registers (NTB Secondary Side) ................................... 238
3.20.1 Configuration Register Map (NTB Secondary Side) .................................... 238
3.20.2 Standard PCI Configuration Space (0x0 to 0x3F) - Type 0 Common
Configuration Space ............................................................................. 240
3.20.2.1 VID: Vendor Identification Register ......................................... 240
3.20.2.2 DID: Device Identification Register (Dev#N, PCIE NTB Sec Mode) 240
3.20.2.3 PCICMD: PCI Command Register (Dev#N, PCIE NTB Sec Mode) .. 241
3.20.2.4 PCISTS: PCI Status Register................................................... 243
3.20.2.5 RID: Revision Identification Register........................................ 245
3.20.2.6 CCR: Class Code Register....................................................... 245
3.20.2.7 CLSR: Cacheline Size Register ................................................ 246
3.20.2.8 PLAT: Primary Latency Timer.................................................. 246
3.20.2.9 HDR: Header Type Register (Dev#3, PCIe NTB Sec Mode).......... 246
3.20.2.10 BIST: Built-In Self Test.......................................................... 247
3.20.2.11 SB01BASE: Secondary BAR 0/1 Base Address (PCIE NTB Mode).. 247
3.20.2.12 SB23BASE: Secondary BAR 2/3 Base Address (PCIE NTB Mode).. 248