Datasheet
Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
82 Order Number: 323103-001
The Intel
®
Xeon
®
processor C5500/C3500 series supports software initiated T-state
throttling and automatic T-state throttling as part of the internal Thermal Monitor
response mechanism (upon TCC activation). The PECI T-state throttling control register
read/write capability is managed only in the PECI domain. In-band software may not
manipulate or read the PECI T-state control setting. In the event that multiple agents
are requesting T-state throttling simultaneously, the CPU always gives priority to the
lowest power setting, or the numerically lowest duty cycle.
On the Intel
®
Xeon
®
processor C5500/C3500 series, the only supported duty cycle is
12.5% (12.5% clocks on, 87.5% clocks off). It is expected that T-state throttling will
be engaged only under emergency thermal or power conditions. Future products may
support more duty cycles, as defined in the following table.
The T-state control word is defined as follows:
2.2.2.7 MbxSend()
The MbxSend() command is utilized for sending requests to the generic Mailbox
interface. Those requests are in turn serviced by the processor with some nominal
latency and the result is deposited in the mailbox for reading. MbxGet() is used to
retrieve the response and details are documented in Section 2.2.2.8.
The details of processor mailbox capabilities are described in Section 2.2.2.6.1, and
many of the fundamental concepts of Mailbox ownership, release, and management are
discussed in Section 2.2.2.9.
2.2.2.7.1 Write Data
Regardless of the function of the mailbox command, a request type modifier and 4-byte
data payload must be sent. For Mailbox commands where the 4-byte data field is not
applicable (e.g., the command is a read), the data written should be all zeroes.
Table 37. ACPI T-State Duty Cycle Definition
Duty Cycle Code Definition
0x0 Undefined
0x1 12.5% clocks on / 87.5% clocks off
0x2 25% clocks on / 75% clocks off
0x3 37.5% clocks on / 62.5% clocks off
0x4 50% clocks on / 50% clocks off
0x5 62.5% clocks on / 37.5% clocks off
0x6 75% clocks on / 25% clocks off
0x7 87.5% clocks on / 12.5% clocks off
Figure 25. ACPI T-State Throttling Control Read / Write Definition
Enable
Duty Cycle
Reserved
70
0xB / 0xC
Request Type
Request Data
543 107
1 2 3 4Byte # 0
Data