Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 81
Interfaces
2.2.2.6.9 T-State Throttling Control Read / Write
PECI offers the ability to enable and configure ACPI T-state (core clock modulation)
throttling. ACPI T-state throttling forces all CPU cores into duty cycle clock modulation
where the core toggles between C0 (clocks on) and C1 (clocks off) states at the
specified duty cycle. This throttling reduces CPU performance to the duty cycle
specified and, more importantly, results in processor power reduction.
Table 36. Machine Check Bank Definitions
Bank Number Bank Index Meaning
0 0 MC0_CTL[31:0]
0 1 MC0_CTL[63:32]
0 2 MC0_STATUS[31:0]
0 3 MC0_STATUS[63:32]
0 4 MC0_ADDR[31:0]
0 5 MC0_ADDR[63:32]
0 6 MC0_MISC[31:0]
0 7 MC0_MISC[63:32]
1 0 MC1_CTL[31:0]
1 1 MC1_CTL[63:32]
1 2 MC1_STATUS[31:0]
1 3 MC1_STATUS[63:32]
1 4 MC1_ADDR[31:0]
1 5 MC1_ADDR[63:32]
1 6 MC1_MISC[31:0]
1 7 MC1_MISC[63:32]
6 0 MC6_CTL[31:0]
6 1 MC6_CTL[63:32]
6 2 MC6_STATUS[31:0]
6 3 MC6_STATUS[63:32]
6 4 MC6_ADDR[31:0]
6 5 MC6_ADDR[63:32]
6 6 MC6_MISC[31:0]
6 7 MC6_MISC[63:32]
8 0 MC8_CTL[31:0]
8 1 MC8_CTL[63:32]
8 2 MC8_STATUS[31:0]
8 3 MC8_STATUS[63:32]
8 4 MC8_ADDR[31:0]
8 5 MC8_ADDR[63:32]
8 6 MC8_MISC[31:0]
8 7 MC8_MISC[63:32]