Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
8 Order Number: 323103-001
3.19 PCI Express Configuration Registers (NTB Primary Side) .......................................170
3.19.1 Configuration Register Map (NTB Primary Side).........................................170
3.19.2 Standard PCI Configuration Space (0x0 to 0x3F) - Type 0 Common
Configuration Space..............................................................................175
3.19.2.1 VID: Vendor Identification Register..........................................175
3.19.2.2 DID: Device Identification Register (Dev#3, PCIE NTB Pri Mode)..175
3.19.2.3 PCICMD: PCI Command Register (Dev#3, PCIE NTB Pri Mode) ....176
3.19.2.4 PCISTS: PCI Status Register ...................................................178
3.19.2.5 RID: Revision Identification Register ........................................180
3.19.2.6 CCR: Class Code Register.......................................................180
3.19.2.7 CLSR: Cacheline Size Register.................................................181
3.19.2.8 PLAT: Primary Latency Timer ..................................................181
3.19.2.9 HDR: Header Type Register (Dev#3, PCIe NTB Pri Mode)............181
3.19.2.10 BIST: Built-In Self Test ..........................................................182
3.19.2.11 PB01BASE: Primary BAR 0/1 Base Address ...............................182
3.19.2.12 PB23BASE: Primary BAR 2/3 Base Address ...............................183
3.19.2.13 PB45BASE: Primary BAR 4/5 Base Address ...............................184
3.19.2.14 SUBVID: Subsystem Vendor ID (Dev#3, PCIE NTB Pri Mode) ......184
3.19.2.15 SID: Subsystem Identity (Dev#3, PCIE NTB Pri Mode) ...............185
3.19.2.16 CAPPTR: Capability Pointer .....................................................185
3.19.2.17 INTL: Interrupt Line Register ..................................................185
3.19.2.18 INTPIN: Interrupt Pin Register.................................................186
3.19.2.19 MINGNT: Minimum Grant Register ...........................................186
3.19.2.20 MAXLAT: Maximum Latency Register........................................186
3.19.3 Device-Specific PCI Configuration Space - 0x40 to 0xFF.............................187
3.19.3.1 MSICAPID: MSI Capability ID..................................................187
3.19.3.2 MSINXTPTR: MSI Next Pointer.................................................187
3.19.3.3 MSICTRL: MSI Control Register ...............................................187
3.19.3.4 MSIAR: MSI Address Register..................................................189
3.19.3.5 MSIDR: MSI Data Register......................................................190
3.19.3.6 MSIMSK: MSI Mask Bit Register ..............................................191
3.19.3.7 MSIPENDING: MSI Pending Bit Register....................................191
3.19.3.8 MSIXCAPID: MSI-X Capability ID.............................................191
3.19.3.9 MSIXNXTPTR: MSI-X Next Pointer............................................192
3.19.3.10 MSIXMSGCTRL: MSI-X Message Control Register.......................192
3.19.3.11 TABLEOFF_BIR: MSI-X Table Offset and BAR Indicator Register
(BIR).....................................................................................193
3.19.3.12 PBAOFF_BIR: MSI-X Pending Array Offset and BAR Indicator.......193
3.19.3.13 PXPCAPID: PCI Express Capability Identity Register ...................194
3.19.3.14 PXPNXTPTR: PCI Express Next Pointer Register .........................194
3.19.3.15 PXPCAP: PCI Express Capabilities Register ................................195
3.19.3.16 DEVCAP: PCI Express Device Capabilities Register .....................196
3.19.3.17 DEVCTRL: PCI Express Device Control Register (Dev#3, PCIE NTB
Pri Mode) ...............................................................................198
3.19.3.18 DEVSTS: PCI Express Device Status Register ............................200
3.19.3.19 PBAR23SZ: Primary BAR 2/3 Size............................................201
3.19.3.20 PBAR45SZ: Primary BAR 4/5 Size............................................201
3.19.3.21 SBAR23SZ: Secondary BAR 2/3 Size........................................202
3.19.3.22 SBAR45SZ: Secondary BAR 4/5 Size........................................202
3.19.3.23 PPD: PCIE Port Definition........................................................203
3.19.3.24 PMCAP: Power Management Capabilities Register.......................204
3.19.3.25 PMCSR: Power Management Control and Status Register ............205
3.19.4 PCI Express Enhanced Configuration Space ..............................................206
3.19.4.1 VSECPHDR: Vendor Specific Enhanced Capability Header............206
3.19.4.2 VSHDR: Vender Specific Header ..............................................207
3.19.4.3 UNCERRSTS: Uncorrectable Error Status ..................................207
3.19.4.4 UNCERRMSK: Uncorrectable Error Mask....................................208
3.19.4.5 UNCERRSEV: Uncorrectable Error Severity................................209
3.19.4.6 CORERRSTS: Correctable Error Status......................................210