Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 79
Interfaces
These status bits are a subset of the bits defined in the IA32_THERM_STATUS MSR on
the processor, and more details on the meaning of these bits may be found in the
Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Vol. 3B.
Both status and sticky log bits are managed in this status word. All sticky log bits are
set upon a rising edge of the associated status bit, and the log bits are cleared only by
Thermal Status reads or a processor reset. A read of the Thermal Status Word always
includes a log bit clear mask that allows the host to clear any or all log bits that it is
interested in tracking.
A bit set to 0b0 in the log bit clear mask will result in clearing the associated log bit. If
a mask bit is set to 0b0 and that bit is not a legal mask, a failing completion code will
be returned. A bit set to 0b1 is ignored and results in no change to any sticky log bits.
For example, to clear the TCC Activation Log bit and retain all other log bits, the
Thermal Status Read should send a mask of 0xFFFFFFFD.
2.2.2.6.4 Counter Snapshot / Read / Clear
A reference time and ‘Thermally Constrained’ time are managed in the processor. These
two counters are managed via the Mailbox. These counters are valuable for detecting
thermal runaway conditions where the TCC activation duty cycle reaches excessive
levels.
The counters may be simultaneously snapshot, simultaneously cleared, or
independently read. The simultaneous snapshot capability is provided in order to
guarantee concurrent reads even with significant read latency over the PECI bus. Each
counter is 32 bits wide.
Figure 22. Thermal Status Word
Critical Temperature Log
Critical Temperature Status
Bidirectional PROCHOT# Log
Bidirectional PROCHOT#
Status
TCC Activation Log
TCC Activation Status
3
1
6543210
Reserved
Table 35. Counter Definition
Counter Name
Counter
Number
Definition
Total Time 0x00
Counts the total time the processor has been executing with a
resolution of approximately 1ms. This counter wraps at 32 bits.
Thermally Constrained Time 0x01
Counts the total time the processor has been operating at a
lowered performance due to TCC activation. This timer includes
the time required to ramp back up to the original P-state target
after TCC activation expires. This timer does not include TCC
activation time as a result of an external assertion of
PROCHOT#.