Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 77
Interfaces
Multi-Domain Support: Yes (see Table 41)
Description: Writes the data sent to the requested register address. Write Length
dictates the desired write granularity. The command always returns a completion code
indicating the pass/fail status information. Write commands issued to illegal Bus
Numbers, or unimplemented Device / Function / Register addresses are ignored but
return a passing completion code. See Section 2.2.4.2 for details regarding completion
codes.
The 4-byte PCI configuration address and data defined above are sent in standard PECI
ordering with LSB first and MSB last.
2.2.2.5.2 Supported Responses
The typical client response is a passing FCS, a passing Completion Code and valid Data.
Under some conditions, the client’s response will indicate a failure.
2.2.2.6 Mailbox
The PECI mailbox (“Mbx”) is a generic interface to access a wide variety of internal
processor states. A Mailbox request consists of sending a 1-byte request type and
4-byte data to the processor, followed by a 4-byte read of the response data. The
following sections describe the Mailbox capabilities as well as the usage semantics for
the MbxSend and MbxGet commands which are used to send and receive data.
Figure 21. PCIConfigWr()
Byte #
Byte
Definition
0
Client Address
1
Write Length
{0x07,0x08,0x10}
2
Read Length
0x01
WL+1
FCS
3
Cmd Code
0xc5
WL+2
Completion
Code
WL+3
FCS
4 5 6 7
LSB MSBPCI Configuration Address
8 WL-1
LSB MSBData (1, 2 or 4 bytes)
WL
AW FCS
Table 33. PCIConfigWr() Response Definition
Response Meaning
Bad FCS Electrical error or AW FCS failure
Abort FCS Illegal command formatting (mismatched RL/WL/Command Code)
CC: 0x40 Command passed, data is valid
CC: 0x80 Error causing a response timeout. Either due to a rare, internal timing condition or a
processor RESET condition or processor S1 state. Retry is appropriate outside of the RESET
or S1 states.