Datasheet
Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
76 Order Number: 323103-001
2.2.2.4.2 Supported Responses
The typical client response is a passing FCS, a passing Completion Code (CC) and valid
Data. Under some conditions, the client’s response will indicate a failure.
2.2.2.5 PCIConfigWr()
The PCIConfigWr() command gives sideband write access to the PCI configuration
space maintained in the processor. The exact listing of supported devices, functions is
defined below in Table 32. PECI originators may conduct a device/function/register
enumeration sweep of this space by issuing reads in the same manner that BIOS
would.
PCI configuration addresses are constructed as shown in Figure 19, and this command
is subject to the same address configuration rules as defined in Section 2.2.2.4. PCI
configuration reads may be issued in byte, word, or dword granularities.
Because a PCIConfigWr() results in an update to potentially critical registers inside the
processor, it includes an Assured Write FCS (AW FCS) byte as part of the write data
payload. See the RS - Platform Environment Control Interface (PECI) Specification,
Revision 2.0 for a definition of the AW FCS protocol. In the event that the AW FCS
mismatches with the client-calculated FCS, the client will abort the write and will
always respond with a bad Write FCS.
2.2.2.5.1 Command Format
The PCIConfigWr() format is as follows:
Write Length: 7 (byte), 8 (word), 10 (dword)
Read Length: 1
Command: 0xc5
Table 31. PCIConfigRd() Response Definition
Response Meaning
Abort FCS Illegal command formatting (mismatched RL/WL/Command Code)
CC: 0x40 Command passed, data is valid
CC: 0x80 Error causing a response timeout. Either due to a rare, internal timing condition or a
processor RESET or processor S1 state. Retry is appropriate outside of the RESET or
S1 states.
Table 32. PCIConfigWr() Device/Function Support
Writable
Description
Device Function
21Intel
®
QuickPath Interconnect Link 0 Intel
®
IBIST
25Intel
®
QuickPath Interconnect Link 1 Intel
®
IBIST
3 4 Memory Controller Intel
®
IBIST
1
1. Currently not available for access through the PECI PCIConfigWr() command.
4 3 Memory Controller Channel 0 Thermal Control / Status
5 3 Memory Controller Channel 1 Thermal Control / Status
6 3 Memory Controller Channel 2 Thermal Control / Status