Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 75
Interfaces
255 for legacy processor and 254 for non-legacy processor. The client will return all 1’s
in the data response and ‘pass’ for the completion code for all of the following
conditions:
• Unimplemented Device
• Unimplemented Function
• Unimplemented Register
PCI configuration reads may be issued in byte, word, or dword granularities.
2.2.2.4.1 Command Format
The PCIConfigRd() format is as follows:
Write Length: 5
Read Length: 2 (byte data), 3 (word data), 5 (dword data)
Command: 0xc1
Multi-Domain Support: Yes (see Table 41)
Description: Returns the data maintained in the PCI configuration space at the PCI
configuration address sent. The Read Length dictates the desired data return size. This
command supports byte, word, and dword responses as well as a completion code. All
command responses are prepended with a completion code that includes additional
pass/fail status information. See Section 2.2.4.2 for details regarding completion
codes.
The 4-byte PCI configuration address defined above is sent in standard PECI ordering
with LSB first and MSB last.
Figure 19. PCI Configuration Address
31
Reserved
2728 20 19 15 1114 12 0
Bus Device Function Register
Figure 20. PCIConfigRd()
Byte #
Byte
Definition
0
Client Address
1
Write Length
0x05
2
Read Length
{0x02,0x03,0x05}
8
FCS
3
Cmd Code
0xc1
9
Completion
Code
10
Data 0 ...
8+RL
Data N
9+RL
FCS
4 5 6 7
LSB MSBPCI Configuration Address