Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 7
2.7.1 DMI Error Flow..................................................................................... 134
2.7.2 Processor/PCH Compatibility Assumptions................................................ 134
2.7.3 DMI Link Down .................................................................................... 134
3.0 PCI Express Non-Transparent Bridge..................................................................... 135
3.1 Introduction ................................................................................................... 135
3.2 NTB Features Supported on Intel
®
Xeon
®
Processor C5500/C3500 Series............... 135
3.2.1 Features Not Supported on the Intel
®
Xeon
®
Processor C5500/C3500 Series
NTB.................................................................................................... 136
3.3 Non-Transparent Bridge vs. Transparent Bridge................................................... 136
3.4 NTB Support in Intel
®
Xeon
®
Processor C5500/C3500 Series................................ 139
3.5 NTB Supported Configurations .......................................................................... 139
3.5.1 Connecting Intel
®
Xeon
®
Processor C5500/C3500 Series Systems
Back-to-Back with NTB Ports.................................................................. 139
3.5.2 Connecting NTB Port on Intel
®
Xeon
®
Processor C5500/C3500 Series to Root
Port on Another Intel
®
Xeon
®
Processor C5500/C3500 Series System -
Symmetric Configuration....................................................................... 140
3.5.3 Connecting NTB Port on Intel
®
Xeon
®
Processor C5500/C3500 Series to Root
Port on Another System - Non-Symmetric Configuration............................ 141
3.6 Architecture Overview...................................................................................... 143
3.6.1 “A Priori” Configuration Knowledge ......................................................... 146
3.6.2 Power On Sequence for RP and NTB........................................................ 146
3.6.3 Crosslink Configuration ......................................................................... 146
3.6.4 B2B BAR and Translate Setup ................................................................ 149
3.6.5 Enumeration and Power Sequence.......................................................... 150
3.6.6 Address Translation.............................................................................. 152
3.6.6.1 Direct Address Translation...................................................... 152
3.6.7 Requester ID Translation....................................................................... 155
3.6.8 Peer-to-Peer Across NTB Bridge ............................................................. 157
3.7 NTB Inbound Transactions................................................................................ 158
3.7.1 Memory, I/O and Configuration Transactions............................................ 158
3.7.2 Inbound PCI Express Messages Supported............................................... 159
3.7.2.1 Error Reporting..................................................................... 159
3.8 Outbound Transactions .................................................................................... 160
3.8.1 Memory, I/O and Configuration Transactions............................................ 160
3.8.2 Lock Support ....................................................................................... 161
3.8.3 Outbound Messages Supported .............................................................. 161
3.8.3.1 EOI..................................................................................... 163
3.9 32-/64-Bit Addressing...................................................................................... 163
3.10 Transaction Descriptor ..................................................................................... 163
3.10.1 Transaction ID..................................................................................... 163
3.10.2 Attributes............................................................................................ 164
3.10.3 Traffic Class......................................................................................... 165
3.11 Completer ID.................................................................................................. 165
3.12 Initialization ................................................................................................... 165
3.12.1 Initialization Sequence with NTB Ports Connected Back-to-Back (NTB/NTB).. 165
3.12.2 Initialization Sequence with NTB Port Connected to Root Port..................... 166
3.13 Reset Requirements......................................................................................... 167
3.14 Power Management ......................................................................................... 167
3.15 Scratch Pad and Doorbell Registers.................................................................... 167
3.16 MSI-X Vector Mapping ..................................................................................... 169
3.17 RAS Capability and Error Handling ..................................................................... 169
3.18 Registers and Register Description..................................................................... 169
3.18.1 Additional Registers Outside of NTB Required (Per Stepping)...................... 169
3.18.2 Known Errata (Per Stepping) ................................................................. 169
3.18.3 Bring Up Help ...................................................................................... 170