Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 69
Interfaces
2.2 Platform Environment Control Interface (PECI)
The Platform Environment Control Interface (PECI) uses a single wire for self-clocking
and data transfer. The bus requires no additional control lines. The physical layer is a
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on whether the bit
value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established
with every message. In this way, it is flexible even though underlying logic is simple.
The interface design was optimized for interfacing to Intel processor and chipset
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
The PECI bus offers:
• A wide speed range from 2 Kbps to 2 Mbps.
MC_THROTTLE_OFFSET RANK 8 Throttler
Compared against bits [36:29] of
virtual temperature to determine the
throttle point. Recommended value is
255.
MC_COOLING_COEF YES RANK 8 Throttler
Heat removed from DRAM in 8 DCLKs.
This should be scaled relative to the
per command weights and the initial
value of the throttling threshold. This
includes idle command and refresh
energies. If 2X refresh is supported,
the worst case of 2X refresh must be
assumed. This parameter may be
modified during operation.
MC_CLOSED_LOOP YES REF_2X_NOW 1 Throttler
When set, refresh rate is doubled.
This parameter may be modified
during operation.
Table 28. Thermal Throttling Status Fields
Register Parameter Bits One Per Description
MC_DDR_THERM_STATUS STATE 1
Socket. (appears
in each of the 3
channels)
DDR_THERM# rising edge was detected since
this bit was last reset. Parameter appears on
B-x stepping silicon.
DDR_THERM# falling edge was detected since
this bit was last reset.
Current value of DDR_THERM# pin
MC_THERMAL_STATUS RANK_TEMP 4 Channel
Bit specifies whether the rank is above
throttling threshold.
MC_THERMAL_STATUS CYCLES_THROTTLED 16 Channel
The number of throttle cycles triggered in all
ranks since last temperature sample
MC_RANK_VIRTUAL_TEMP RANK 8 Throttler
Most significant bits of Virtual Temperature of
the selected rank. The difference between the
Virtual Temperature and the Sensor
temperature can be used to determine how
fast fan speed should be increased.
Table 27. Thermal Throttling Control Fields (Sheet 2 of 2)
Register
Dynamically
Validated
Parameter Bits One per Description