Datasheet
Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
66 Order Number: 323103-001
Integrated Memory Controller can double the refresh rate dynamically in two cases:
• When MC_CLOSED_LOOP.REF_2X_NOW configuration bit is set.
• When DDR_THERM# pin is asserted and bit[2] of the
MC_DDR_THERM_COMMANDX register is set.
Memory controller delays refresh when doubling 2x refresh rate and ASR_PRESENT bit
is set.
Memory controller supports a register based dynamic 2X Refresh via the REF_2X_NOW
bit in the MC_CLOSED_LOOP register. See the MC_CLOSED_LOOP register in Table 27
for more details. In a system ensuring the DRAM never exceeds T64, it is conceivable
the DIMM temperature sensor be used for this purpose. However, most platforms
reduce fan speed during idle periods, and fan speed cannot be increased fast enough to
keep up with DRAM temperature. Therefore, DIMM temperature sensors are probably
used for T64. A temperature sensor near the DIMMs can be used to control 2X refresh.
Alternatively, code running on a processor or an external agent via PECI can set the
MC_CLOSED_LOOP.REF_2X_NOW configuration bit on a channel basis. An agent which
monitors the DIMM temperature serially via SPD can track this temperature. The agent
must account for its worst case update interval and max rate of DRAM temperature
increase to make sure the DRAM does not exceed T32 between updates. There is no
failsafe logic to apply 2X Refresh if updates are not received often enough.
If the agent cannot reliably monitor this information, the refresh rate should be
statically doubled by setting refresh parameters for extended temperature DRAM.
2.1.14.9 Demand Observation
In order to smooth fan speed transitions, the fan control agent needs to know how
memory activity demanded by the current application is related to the throttling point.
By observing the trend of Virtual Temperature relative to throttling point, the fan
controller can determine the trend of demand before the throttling point is exceeded.
However, once the throttling point has been exceeded, the Virtual Temperature will
remain at the throttling point and only provides the information that demand exceeds
the throttling limit.
If the fan controller could determine the throttling duty cycle, it could determine how
much demand exceeds the throttling limit. Therefore, the CYCLES_THROTTLED field
gives an indication of throttling duty cycle. A 32-bit counter accumulates the number of
DCLKs each rank has been throttled. Each time the ZQ interval completes, the 16 most
significant bits of the counter are loaded into the status register and the counter is
cleared. The register thus holds the number of cycles throttled in the last 128 ms (give
or take a factor of 2; the thermal sensor sample rate is configurable).
Platform or some DRAM
on the socket does not
support ETR. DRAM
temperatures are limited
to 85 degrees.
Refresh interval is always tREFI. There is no 2x refresh response. Self refresh entry is not delayed.
Refresh rate is always 1x.
All DRAM on the socket
and the platform
support ERT. Throttling
does not limit DRAM
temperature below
88 degrees.
BIOS will halve tREFI and double the parameters
controlling maintenance operations. The memory
controller and the DRAM are configured to refresh at
2x rate. There is no dynamic 2x refresh response.
When DDR_THERM# pin defined to respond
with 2x refresh is inactive, refresh interval
returns to tREFI.
Non-ASR DRAM that supports Extended Temperature will be configured to self refresh at 2x rate.
Non-ASR DRAM that does not support Extended Temperature is configured to self-refresh at 1x rate.
ASR DRAM will be configured to adjust its self-refresh rate according to temperature.
Table 24. Refresh for Different DRAM Types
Type Open Loop Closed Loop