Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 65
Interfaces
unrestrained BW such that the average over many seconds is that which is thermally
supported. The choppiness will be lessened by configuring MinThottleDutyCycle no
lower than that required by the specific DIMMs plugged into each system.
2.1.14.7 Advanced Throttling Options
There are two closed loop throttling considerations which can be addressed by a
thermal control agent (Management Hardware via PECI or SW periodically running on a
core).
Option 1 is that all channels are throttled when any DIMM is hot. The CPU prefetchers
adapt to longer latencies caused by throttling one rank by reducing the bandwidth to
that rank. So it is better to throttle only the hot ranks.
Option 2 is the closed "transient margin": The DIMM temperature sensor lags the DRAM
die temperature, so throttling must be triggered at a lower temperature than T64. This
results in a loss of bandwidth for a given cooling capability.
A thermal control agent which monitors the DIMM temperature serially via SPD can
collect higher granularity (as opposed to binary hot/cold via DDR_THERM#)
information. The thermal control agent can set the ThrottleNow bits for ranks that are
nearing max temperature. Per rank throttling only limits bandwidth to hot DIMMs.
Both concerns can be addressed by a thermal control agent modulating the virtual
temperature sensor as described in Section 2.1.14.5.5, “Cooling Coefficient” . When
this is done, closed loop throttling can be enabled at a higher DIMM temperature that
does not include the transient margin can be feedback should not be needed, but can
be added for safety.
2.1.14.8 2X Refresh
Some DRAMs can be operated above 85 degrees if refresh rate is doubled. The DDR3
DRAM spec refers to this capability as Extended Temperature Range (ETR). Some
DRAMs have the capability to self refresh at a rate appropriate for their temperature.
The DDR3 spec defines this as the Automatic Self Refresh (ASR) feature. When all
DRAM on a channel have ASR enabled, the
MC_CHANNEL_X_REFRESH_THROTTLE_SUPPORT.ASR_PRESENT bit should be set.
Some platforms may support Extended Temperature Range operation, others may not.
The following recommendations are predicated on the assumption that BIOS set the
DRAM ASR enable for any DIMM with SPD that indicates ASR support.
Table 24. Refresh for Different DRAM Types
Type Open Loop Closed Loop
No indication of ETR
ETR is indicated by DDR_THERM# or
MC_CLOSED_LOOP.REF_2X_NOW. The
temperature indication can be directly from
a thermal sensor, or via Baseboard
Management Controller (BMC), or software.