Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
64 Order Number: 323103-001
2.1.14.5.7 Response to Throttling Trigger
When throttling is triggered, CKE will be de-asserted. DRAM issue will be suppressed to
the hot rank except for refreshes. After 256 DCLKs, command issue will be allowed
according to the MinThrottleDutyCycle field. After that, command issue will be
permitted if temperature is above threshold.
This should be the case as the worst case cooling after 256 DCLKs of precharge power
down should be sufficient to allow many commands. In the steady state under TDP
load, 256 DCLKs of inactivity will be followed by however many DCLKs of high activity
can be thermally sustained, and then another 256 DCLKs of inactivity and the sequence
repeats.
Throttling is not re-triggerable, that is, multiple throttling triggers during the 256 DCLK
interval will have no effect.
To support Lockstep mode, ranks on each channel will be throttled if throttling is
required for the corresponding rank on the other channel.
2.1.14.5.8 DDR_THERM# Pin Response
A DDR_THERM# pin on the socket enables the throttle response.
The interrupt capability is intended to allow modulation of throttling parameters by
software that cannot perform a control loop several times a second. There is no PCI
device to associate with the interrupts generated. The DDR_THERM# status registers
have to be examined in response to these interrupts to determine whether the memory
controller has triggered the interrupt.
2.1.14.6 Closed Loop Thermal Throttling (CLTT)
Basic closed loop thermal throttling can be achieved using the DDR_THERM# signal.
Temperature sensors in Tcrit only mode will be placed on or near the DIMMs attached to
the socket. The EVENT# pin of all DIMMs will be wired-OR to produce a DDR_THERM#
signal to the Memory Controller. The temperature sensors will be configured to trip at
the lowest temperature at which the associated DRAMs might exceed T64 or T32
(double or single refresh DRAM temperature spec) case temperature. BIOS or firmware
will calculate and configure DIMM Event# temperature limit (Tcrit) based on DIMM
thermal/power property, system cooling capacity, and DRAM/register temperature
specifications. These temperature sensors are generally updated a minimum of eight
times per second, but the more often they update, the smoother the throttling will be.
When one of the temperature sensors trips, the memory controller will throttle all ranks
according to the duty cycle configured in the MinThrottleDutyCycle fields. This field
should be set to allow a percentage of full bandwidth supported by the minimum fan
speed at worst case operating conditions. Command issue will be blocked for the Off
portion of the duty cycle whether or not commands have been issued during the On
portion. This will generally result in over-throttling until the temperature sensors re-
evaluate. This will result in choppy throttling. For a temp sensor update interval of 1/8
second. There will be 125 ms of very low bandwidth followed by n*125 ms of
Table 23. DDR_THERM# Responses
Register Parameter Bits One Per Description
MC_DDR_THERM_COMMAND THROTTLE 1
Socket.
(appears in each
of the three
channels)
While DDR_THERM# is high, Duty Cycle throttling will
be imposed on all channels. The platform should ensure
DDR_THERM# is high when any DIMM is over T64.