Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 61
Interfaces
2.1.14.4 Static DRAM Interface Power Savings Features
Disable bits in the padscan registers are available to disable categories of pins.
2.1.14.5 DRAM Temperature Throttling
The Integrated Memory Controller currently supports open loop and closed loop
throttling. The open loop throttling is compatible with the virtual temperature sensor
approach implemented in desktop and mobile chipsets.
2.1.14.5.1 Throttler Logic Overview
There are 12 throttlers, four for each channel. The throttlers can be used in three
modes, defined by what triggers throttling: a Virtual Temp Sensor (VTS), a ThrottleNow
configuration bit, or a DDR_THERM# signal. Virtual Temperature Sensor is used where
no DRAM temperature information is available. DDR_THERM# signal is used for basic
closed loop throttling without any software assist. ThrottleNow mode allows software
running on the CPU or thermal management agents to achieve maximum performance
in varying operating conditions.
Each throttler has a VTS, ThrottleNow bit, and duty cycle generator. The DDR_THERM#
signal is applied to all throttlers. The throttlers are mapped to ranks as described later.
Disable mixer and amp in phase
interpolators for data drivers
No data to drive.
Derived from write
CAS.
1 DCLK Driving data 1 DCLK
Power down Data Receivers, Strobe
Phase Interpolators, Strobe amplifiers,
Receive enable logic
No data to receive 1 DCLK Receiving data 1 DCLK
Disable ODT No data to receive 2 DCLK Receiving data 2 DCLK
Clock disable
PCU warns clocks
will be removed
after DRAMs in self
refresh.
10 DCLK
PCU indicates clocks
are stable.
1 usec
Table 22. Dynamic IO Power Savings Features (Sheet 2 of 2)
Power Savings Feature On Condition Time to Turn Off Off Condition Time to Turn On