Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
6 Order Number: 323103-001
2.5.11.2 Coherent Write Flow ..............................................................117
2.5.11.3 Eviction Policy.......................................................................117
2.5.12 Outgoing Request Buffer (ORB) ..............................................................118
2.5.13 Time-Out Counter.................................................................................118
2.6 PCI Express Interface.......................................................................................119
2.6.1 PCI Express Architecture........................................................................119
2.6.1.1 Transaction Layer..................................................................120
2.6.1.2 Data Link Layer.....................................................................120
2.6.1.3 Physical Layer.......................................................................120
2.6.2 PCI Express Link Characteristics - Link Training, Bifurcation, Downgrading
and Lane Reversal Support ....................................................................120
2.6.2.1 Link Training.........................................................................120
2.6.2.2 Port Bifurcation.....................................................................121
2.6.2.3 Port Bifurcation via BIOS........................................................121
2.6.2.4 Degraded Mode.....................................................................122
2.6.2.5 Lane Reversal .......................................................................123
2.6.3 Gen1/Gen2 Speed Selection...................................................................123
2.6.4 Link Upconfigure Capability....................................................................123
2.6.5 Error Reporting ....................................................................................123
2.6.5.1 Chipset-Specific Vendor-Defined..............................................123
2.6.5.2 ASSERT_GPE / DEASSERT_GPE...............................................124
2.6.6 Configuration Retry Completions.............................................................124
2.6.7 Inbound Transactions............................................................................125
2.6.7.1 Inbound PCI Express Messages Supported................................125
2.6.8 Outbound Transactions..........................................................................126
2.6.8.1 Memory, I/O and Configuration Transactions Supported..............126
2.6.9 Lock Support........................................................................................126
2.6.10 Outbound Messages Supported...............................................................127
2.6.10.1 Unlock .................................................................................127
2.6.10.2 EOI .....................................................................................127
2.6.11 32/64 bit Addressing.............................................................................127
2.6.12 Transaction Descriptor...........................................................................128
2.6.12.1 Transaction ID ......................................................................128
2.6.12.2 Attributes.............................................................................129
2.6.12.3 Traffic Class..........................................................................129
2.6.13 Completer ID .......................................................................................129
2.6.14 Miscellaneous.......................................................................................129
2.6.14.1 Number of Outbound Non-posted Requests...............................129
2.6.14.2 MSIs Generated from Root Ports and Locks...............................129
2.6.14.3 Completions for Locked Read Requests.....................................130
2.6.15 PCI Express RAS...................................................................................130
2.6.16 ECRC Support ......................................................................................130
2.6.17 Completion Timeout..............................................................................130
2.6.18 Data Poisoning .....................................................................................130
2.6.19 Role-Based Error Reporting....................................................................130
2.6.20 Data Link Layer Specifics.......................................................................131
2.6.20.1 Ack/Nak...............................................................................131
2.6.20.2 Link Level Retry ....................................................................131
2.6.21 Ack Time-out .......................................................................................131
2.6.22 Flow Control.........................................................................................131
2.6.22.1 Flow Control Credit Return by IIO............................................133
2.6.22.2 FC Update DLLP Timeout ........................................................133
2.6.23 Physical Layer Specifics .........................................................................133
2.6.23.1 Polarity Inversion ..................................................................133
2.6.24 Non-Transparent Bridge.........................................................................133
2.7 Direct Media Interface (DMI2) ...........................................................................134