Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 59
Interfaces
The delay between ZQ commands and subsequent operations and the rate of ZQCS
commands are defined in the ZQ Timings register. No other commands will be issued
between bank closure and ZQCS.
Initial calibration will be performed by initiating a ZQCL command using the DDR3CMD
register. The ZQCL command initiates a calibration sequence in the DRAM that updates
driver and termination values.
Specific DRAM vendors will specify a rate to initiate ZQCS calibration commands. BIOS
performs the initial calibration using ZQ.
In general, the Integrated Memory Controller will precharge all banks before issuing
ZQCS command.
The Integrated Memory Controller will issue ZQCL on exit from self refresh as required
by the DDR3 spec.
ZQCL for initialization can be issued prior to normal operation by writing the DDRCMD
register.
2.1.14 Power Management
2.1.14.1 Interface to Uncore Power Manager
Each mode in which the Integrated Memory Controller will reduce performance for
power savings will be at the command of the Uncore power manager. The Uncore power
manager will be aware of collective CPU power states, platform power states. It will
request entry into a particular mode and the Integrated Memory Controller will
acknowledge entry. In some cases, entry into a power mode merely enables the
possibility (e.g. DRAM Precharge Power Down Enabled) of entering a low power state;
in other cases, such as Self Refresh, it indicates full entry into the low power state.
2.1.14.2 DRAM Power Down States
2.1.14.2.1 Power-Down
The Integrated Memory Controller will have a configurable activity timeout for each
rank. Whenever no activities are present to a given rank for the configured interval, the
Integrated Memory Controller will transition the rank to power-down mode.
The maximum duration for either active or precharge power-down is limited by the
refresh requirements of the device tRFC(max). The minimum duration for power-down
entry and exit is limited by the tCKE(min) parameter.
The Integrated Memory Controller will transition the DRAM to Power-down by de-
asserting CKE and driving a NOP command. The Integrated Memory Controller will
tristate all DDR interface pins except CKE (de-asserted) and ODT while in power down.
The Integrated Memory Controller will transition the DRAM out of power-down state by
synchronously asserting CKE and driving a NOP command.
2.1.14.2.2 Active Power Down
The DDR frequency and supply voltage cannot be changed while the DRAM is in active
power-down.
CKE will be de-asserted CKE idle clocks after most recent command to a Rank. It takes
two clocks to exit. The DRAM can only remain in Active Power Down for 9*tREFI
(~700 µsec).