Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
58 Order Number: 323103-001
2.1.11.4 Supported Configurations
The following table defines the DDR3 organizations that the Integrated Memory
Controller supports.
2.1.12 DDR Protocol Support
The Integrated Memory Controller will use burst length of 4 for lockstep and 8 for
independent channels. The Integrated Memory Controller will not vary burst length
during operation.
2.1.13 Refresh
The Integrated Memory Controller will issue refreshes when no commands are pending
to a rank. It will refresh all banks within a rank at the same time. It will not use per-
bank refresh.
The refresh engine satisfies the following requirements:
Once DRAM initialization is complete, each DRAM gets at least N-8 and no more than N
refreshes in any interval of length N * 7.8 us.
• Until the time when timing constraints and the previous requirements force refresh
issue, no refreshes are issued to banks for which there are uncompleted reads.
• Support configurable tRFC up to 350 ns.
2.1.13.1 DRAM Driver Impedance Calibration
The ZQ mechanism is used to maintain the impedance of DRAM drivers constant
despite temperature and very low frequency voltage variations.
Table 20. DDR Organizations Supported