Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 57
Interfaces
The mapping of System Address bits to read return transfers are the same for lockstep.
That is, SystemAddress[3] selects the upper/lower portion of the transfer and
SystemAddress[5:4] determine the critical word sequence of transfers.
However, since two channels provide the data in lockstep, the System Address bits are
mapped to different DRAM column bits. SystemAddress[4] determines the channel on
which the data is stored, but not necessarily the channel that returns the data. Both
lockstepped channels have duplicate copies of the entire cache line. The even channels
return the least significant 8B chunks and the odd channels return the most significant
8 B chunks. Thus half of the data returned by one memory channel is stored in the
other channel’s buffers. Data with SystemAddress[3]=1 is driven by odd physical
channels, while data with SystemAddress[3]=0 is driven by even physical channels.
The Integrated Memory Controller is constructed such that SystemAddress[3]
determines which channel drives the data.
SystemAddress[5] is mapped to Column[1] so that the DRAMs return the critical 32 B
codeword first. Column[0] is forced to zero so that every DRAM read returns the 28 B
chunks of each half-codeword in the same order. The burst of four sequences
Column[1:0]. Column[2] selects a different cache line and is mapped to higher order
address bits.
The table below summarizes the lower order bit mapping. It applies to both Open Page
and Closed Page address mappings.
Table 18. Critical Word First Sequence of Read Returns
Transfer Most Significant 8B to GQ Least Significant 8B to GQ
SysAdrs[3]=1 SysAdrs[3]=0
First pair SysAdrs[5], SysAdrs[4] SysAdrs[5], SysAdrs[4]
Second pair SysAdrs[5], !SysAdrs[4] SysAdrs[5], !SysAdrs[4]
Third pair !SysAdrs[5], SysAdrs[4] !SysAdrs[5], SysAdrs[4]
Fourth pair !SysAdrs[5], !SysAdrs[4] !SysAdrs[5], !SysAdrs[4]
Table 19. Lower System Address Bit Mapping Summary
Lockstepped? ECC
Critical
8B first?
Physical
Channel
Col[2] Col[1] Col[0]
Independent
Burst Length of 8
Yes No N/A
Reads:
SysAdrs[5] 0 0
------------------------------------------------------------------
Writes:
0 0 0
No Yes N/A
Reads:
SysAdrs[5] SysAdrs[4] SysAdrs[3]
------------------------------------------------------------------
Writes:
0 0 0
Lockstep
Burst Length of 4
Yes No.
System
Address
[4]
Assigned to a
higher order
SysAdrs bit.
Reads:
SysAdrs[5] 0
------------------------------------------------
Writes:
0 0