Datasheet
Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
56 Order Number: 323103-001
2.1.11.2 Translating Channel Address to Rank Address
This section describes how gaps are removed from the channel address to form a
contiguous address space for each rank. Gaps from one to three cache lines in size
result from interleaving across ranks on a channel. Gaps larger than 512 MB are a
result from the interleaves below.
The Integrated Memory Controller uses DIMM interleaving to balance loads.
Interleaving assigns low order address bits to variable DRAM bits. Since DIMMs on a
channel may be of different sizes, there is not a one to one address mapping. The
larger DIMMs must be split into blocks which are the same size as smaller DIMMs. Thus
the Rank Address space is divided into ranges, each of which may be interleaved
differently.
The channel address may be interleaved across the DIMMs on a channel up to 4 ways.
The channel address is divided into 4 interleave ranges, each of which may be
interleaved differently to support interleave across different sized DIMMs.
The smallest DIMM supported will be 512 MB, which defines the granularity of the
interleave. Each channel maintains 4 range decoders. It specifies which ranks are
interleaved and the offset to be added to the Rank Address address to compensate for
any DRAM addresses used in lower interleaves.
2.1.11.3 Low Order Address Bit Mapping
The mapping of the least significant address bits are affected by:
• whether the request is a read or a write,
• whether channels are lockstepped or independent, and
• whether ECC is enabled.
In general, the mapping is assigned to:
• Return the critical chunk of read data first.
• Simplify the mapping of ECC code bits to DRAM data transfers. When ECC is
enabled, Column bits are zeroed to ensure that the sequence of transfers from the
DRAM to the ECC check is the same for every request.
• Simplify the transfer of write data to the DRAM.
In all cases RankAddress[5:3] is the same as SystemAddress[5:3] and defines the
order in which the Integrated Memory Controller returns data.
Writes are not latency critical and are always written to DRAM starting with chunk 0.
For independent channels, Column[2:0]=0. For lockstep, Column[1:0]=0 and
Column[2] is mapped to a high order System Address bit.
For reads with independent channels and ECC disabled, the critical 8B chunk can be
transferred to the Global Queue before the others. Therefore, Column[2:0] are mapped
to SystemAddress[5:3].
For reads with independent channels and ECC enabled, the 32 B codeword must be
accumulated before forwarding any data. While it reduces latency to get the critical
32 B codeword first, the sequencing of 8 B chunks within the codeword is not
important. Column[1:0] are forced to zero so that every DRAM read returns the 4 8B
chunks of each codeword in the same order. However, read returns are always
transferred in critical word order, so the critical word ordering is performed after the
ECC check.