Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 55
Interfaces
2.1.11 Address Translations
2.1.11.1 Translating System Address to Channel Address
This operation could be considered the final step of Level 1 decode. It removes the
“gaps” introduced by Level 1 decode to produce a contiguous channel address. This
maintains the independence of Level 1 and Level 2 decode. Independence simplifies the
memory mapping problem that must be solved by BIOS. Gap removal is implemented
in the Integrated Memory Controller because Intel
®
QPI does not allow this function to
be performed before remote memory requests are sent to other sockets. The address
that appears on a Intel
®
QPI request must be the system address, not the channel
address.
The maximum number of DIMMs on a channel is three DIMMs. However, maximum
memory capacity is achieved with 2 QR DIMMs, with 12 16 GB DIMMs for a total of
192 GB for the platform with 2 Gb DRAM densities. Higher capacity can be achieved
with 4 Gb DRAMs but 4 Gb DRAMs are not expected to be available for Picket Post
launch.
Unless the channel appears above other channels in the first level decode, the first
address to access the channel will not be 0. As the MMIO gap can be considered a
degenerate 0-way interleave, memory mapped above 4 GB must subtract that gap. If
the channel is interleaved with other channels, the addresses it receives may not be
contiguous.
For example, the set of system addresses that access a 256 MB range of channel
addresses on a given channel may be the even addresses between 1.5 GB and 2 GB.
For any given level 1 interleave, there will be a series of coarse gaps introduced by
lower interleaves and fine gaps introduced by the interleave itself. To keep level 1
decode independent of Level 2 decode, the 1.5GB offset must be subtracted and A[6]
must not be mapped to Channel address bits. In general, it is not sufficient to simply
omit the system address bits not mapped to Channel Address bits.
Level 1 decode performs socket/channel interleave at various granularities. To
compensate, the Level 2 decode must be able to remove any three of the address bits
in Table 18. More significant bits are shifted down. The register that defines the shift for
each interleave has one bit for each address bit to be removed.
The logic that removes the way selection bits from the channel address for a given
channel is independent of the location of the other channels. That is, the address bits to
be removed to close gaps do not depend on whether the other channels of the
interleave appear on the same node or different nodes.
The subtraction and shift operation required is different for each level 1 interleave, so
the level 1 interleave number is passed to the level 2 decode. The second level decode
has configuration registers that hold the offset and bits to be shifted for each level 1
interleave.
After the offset and shift are completed, the set of system addresses that address a
channel are converted to a set of contiguous “Channel Addresses” from 0 to the
number of bytes on the channel.