Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
54 Order Number: 323103-001
2.1.10.2 Second Level Address Translation
Second level address translation converts the channel address resulting from the first
level decode into rank, bank row and column addresses.
The Integrated Memory Controller uses DIMM interleaving to balance loads. The
channel address can be divided into 8 ranges and each range supports an interleave
across 1,2 or 4 ranks. The MC_RIR_LIMIT_CH[2:0]_[7:0] and
MC_RIR_WAYS_CH[2:0]_[31:0] registers define the ranges and rank interleaves.
2.1.10.2.1 Registers
Each channel has the following address mapping registers with the exception of the
lockstep bit, which applies to all.
Table 17. Address Mapping Registers
Register/Bit Description
MC_CHANNEL_MAPPER Register
Channel Mapping Register. Defines the mapping of logical channels
decoded by the first level decode to the physical channels in the
Integrated Memory Controller.
Lockstep bit
Global config bit for all channels. Affects duplication of reads and writes
and address bit mapping.
MC_DOD_CH[2:0]_[1:0]
DIMM Organization Descriptors. Each physical channel has two DOD
registers.
MC_RIR_Limit_CH[2:0]_[7:0]
DIMM Interleave Registers. Defines the range of system addresses that
are directed to each virtual ranks on each physical channel. There are 8
range registers for each channel.
MC_RIR_Ways_CH[2:0]_[31:0]
There are four-way registers for each Rank Interleave Range, one for each
rank that may appear in that range. Each register defines the offset from
channel address to rank address and the combination of address bits used
to select the rank.
RankID DIMM Rank Map Defines which virtual ranks appear on the same DIMM.
Rank Mapping Register Defines the correspondence of virtual ranks to physical CS.