Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 53
Interfaces
2.1.10.1.2 Channel Interleaving
Cache lines (linearly increasing addresses) in an address range can interleave across 1,
2, 3, 4, or 6 memory channels.
2.1.10.1.3 Logical to Physical Channel Mapping
The MC_CHANNEL_MAPPER register and the lockstep bit define the mapping of logical
channels decoded by the first level decode and physical channels in the Integrated
Memory Controller. The MC_CHANNEL_MAPPER register is set to direct reads or writes
from one logical channel to any two physical channels as required for sparing or
mirroring. After the MC_CHANNEL_MAPPER bits take effect, the lockstep bit directs any
read or write that is destined to physical Channel A, to physical Channel B as well.
These bits can be read and written by software. The Integrated Memory Controller will
only modify these bits when a mirrored channel fails. In that case, the bit
corresponding to the failed channel will be cleared.
There is one bit for each physical channel and separate fields for reads and writes. The
least significant bit in each field is for physical channel A. The most significant bit is for
physical channel C. Setting two physical channel write bits indicate that a write should
be sent to both channels. If two bits are set in the write field, the write is sent to both
channels. For mirroring, 2 bits are set in the read field. Reads are directed according to
the hash function: SystemAddress[24] ^ [12] ^ [6].
The following table defines how the lockstep bit and CHM fields are set to steer reads
and writes. In the table, h represents the hash function which evaluates to A or B. The
Logical channel columns show the value of the read (e.g. R=000) and write (e.g.
W=000) fields.
Mirroring consists of duplicating writes to two channels and alternating reads to a pair
of channels. Thus, if any given logical channel has more than one bit for both reads and
writes, they are capable of redundant operation. Mirroring is fully enabled when
software changes the channel state of both channels to redundant, which allows
uncorrectable channel errors to be signaled as correctable. Mirroring is only supported
between channels A-B.
Table 16. Read and Write Steering
Configuration Lockstep
Logical Channel
012
Independent Channel
LCH0 to PCH0,
LCH1 to PCH1,
LCH2 to PCH2
0
W=001
R=001
W=010
R=010
W=100
R=100
Sparing from PCH0 to PCH2.
LCH0 writes to PCH0 and PCH2,
LCH0 reads to PCH0,
LCH1 is mapped to PCH1
0
W=101
R=001
W=010
R=010
W=000
R=000
Mirror PCH0 and PCH1
LCH0 writes to PCH[0] and PCH[2]
LCH0 reads to PCH[2h]
0
W=011
R=011
W=000
R=000
W=000
R=000
Lockstepped
LCH0 to PCH[0] and PCH[1]
1
W=001
R=001
W=000
R=000
W=000
R=000