Datasheet

Testability
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
520 Order Number: 323103-001
14.4 TAP Port Timings
The TAP port timings are shown in Figure 91 and Table 180.
14.5 Boundary-Scan Register Definition
See the Boundary-Scan Description Language (BSDL) file(s) for details about the
boundary-scan register structure, application information, and design warnings.
§ §
Figure 91. Boundary-Scan Port Timing Waveforms
Table 180. Boundary-Scan Signal Timings
Symbol Parameter Min Max Unit Notes
T
JC
Boundary-scan TCK clock period 31.25 ns 32 MHZ
T
JCL
Boundary-scan TCK clock low time 0.4 * T
JC
T
JCH
Boundary-scan TCK clock high time 0.4 * T
JC
T
JSU
Setup of TMS and TDI before TCK rising 8 ns
T
JH
TMS and TDI hold after TCK rising 5 ns
T
JCO
TCK falling to TDO output valid 0.5 7 ns
T
JVZ
TCK falling to TDO output high-impedance 9 ns
T
JRL
Active Boundary-scan Reset Low time 2 T
TCK
TCK
TMS
TDO
T
JC
T
JCH
T
JSU
T
JH
T
JCO
T
JCO
T
JVZ
T
JCL
TRST#
T
JRL
TDI
T
JSU
T
JH