Datasheet
Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
52 Order Number: 323103-001
2.1.10 Memory Address Decode
Memory address decode is the process of taking a system address and converting it to
rank, bank, row and column address on a memory channel. Memory address decode is
performed in two levels. The first level selects the socket (in DP systems) and memory
channel, and generates a channel address. The second level decodes the channel
address into the rank, bank, row and column addresses.
2.1.10.1 First Level Decode
Figure 10 below shows the address decode flow. First the system address is sent to the
Source Address Decoder (SAD) to determine the target socket and Intel
®
QuickPath
Interconnect node ID. The SAD also determines if a transaction will target memory or
MMIO. The remainder of this section assumes the address targets system memory. See
the System Address Decoder Registers in the Uncore (device 0, function 1 in uncore)
and the QPIMADCTRL, QPIMADDATA and QPIPINT registers in the IIO (device 16,
function 1 in the IIO) for details on the programming of the uncore and IIO SAD.
After the requested is routed to the appropriate socket, the Target Address Decoder
(TAD) determines the logical memory channel that will service the request. The TAD
control registers are located in device 3, function 1 in the uncore logic.
The Channel Mapping logic (CHM) is used to determine the physical channel which will
service the request. The operating mode of the memory controller (Independent,
Mirroring, Lockstep) will determine how logical channels are mapped to physical
channels. See the MC_CHANNEL_MAPPER register in device 3, function 0 of the uncore.
Finally, the System Address Gap logic (SAG) is used to “squeeze out the gaps” and
convert the system address to a contiguous set of address for a channel. For example
on a system with a 2 channel interleave, it is possible that a given memory channel
would service every other cacheline with odd cachelines going to one channel and even
cachelines to the other. The SAG translates this every other cacheline system address a
single channel receives to a contiguous set of channel addresses. The channel address
will range from 0 to the number of bytes on that channel minus -1. There is a SAG per
memory channel, see the MC_SAG_CH[2:0]_[7:0] registers in the uncore for
programming details. The channel address that is the output of the SAG is the final
stage of the first level address decode.
2.1.10.1.1 Address Ranges
Level 1 decode supports eight memory ranges. Each range defines a contiguous block
of addresses which target either memory or MMIO (not both). Within a range, there is
only one socket and channel interleave that describes how the addresses are spread
between the memory channels. Different ranges may use different interleaving
schemes.
Figure 10. First Level Address Decode Flow
System
Address
SAD
System
Address +
Target Socket
TAD
System Address +
LogicalChannel
CHM
System Address +
Physical Channel
SAG
Channel Address