Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 519
Testability
The processor uses seven dedicated pins to access the TAP as shown in Figure 90 and
as described in Table 179.
Power must be applied and VCCPWRGOOD_0, VCCPWRGOOD_1 and VTTPWRGOOD
must be driven high prior to using the TAP.
Figure 90. Processor TAP Connections
Note: TDI_M must be connected to TDO_M for
correct operation
TRST#
TCK
TMS
TDO
TDI
TDO_M
PROCESSOR
TDI_M
Table 179. Processor Boundary-Scan TAP Pin Interface
Pin Direction Description
TRST# Input Boundary-scan test reset pin, This signal has an ODT pull-up.
TCK Input
Test clock pin for Boundary-scan TAP Controller and test logic. This signal
has an ODT pull-down.
TMS Input
Boundary-scan Test Mode Select pin. Sampled by the TAP on the Rising
edge of TCK to control the operation of the TAP state machine. It is
recommended that TMS is held high when the Boundary-scan reset is
driven from low to high, to ensure deterministic operation of the test logic.
This signal has an ODT pull-up.
TDI Input
Boundary-scan Test Data Input pin, sampled on the Rising edge of TCK to
provide serial test instructions and data. This signal has an ODT pull-up.
TDO Output
Boundary-scan Test Data Output pin. In inactive drive state except when
instructions or data are being shifted. TDO changes on the falling edge of
TCK. This signal has no pull-up or pull-down.
TDI_M Input
Intermediate Boundary-scan connection. This signal must be connected to
TDO_M for correct operation. This signal has an ODT pull-up.
TDO_M Output
Intermediate Boundary-scan connection. This signal must be connected to
TDI_M for correct operation. This signal has no pull-up or pull-down.