Datasheet

Testability
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
518 Order Number: 323103-001
14.3.4 TAP Interface
This component contains several TAP controllers. The processor’s TAP controllers
connectivity is as follows: TDI --> Processor Un-Core --> Processor Execution Core 0 -
-> Processor Execution Core 1 --> Processor Execution Core 2--> Processor Execution
Core 3--> Processor Integrated I/O --> TDO.
Table 178. Processor Integrated I/O TAP Controller Supported Boundary-Scan
Instruction Opcodes
Opcode
(binary)
Instruction Selected Test Data Register TDR Length
0x00h EXTEST Boundary-scan 115
0x01h
SAMPLE/
PRELOAD (SAMPRE)
Boundary-scan 115
0x02h IDCODE Device Identification 32
0x04h CLAMP Bypass 1
0x05h EXTEST_TOGGLE Boundary-scan 115
0x08h HIGHZ Bypass 1
0xFFh BYPASS Bypass 1
others Reserved
Figure 89. Processor TAP Controller Connectivity
Processor
Un-Core
TDI
Processor
Execution
Core 0
Processor
Execution
Core 1
Processor
Execution
Core 2
TD
O
PROCESSOR
Processor
Execution
Core 3
Processor
Integrated
I/O