Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 517
Testability
14.3 TAP Instructions and Opcodes
The TAP controllers support the boundary-scan instructions listed in:
• Table 176, “Processor Core TAP Controller Supported Boundary-Scan Instruction
Opcodes” on page 517.
• Table 177, “Processor Un-Core TAP Controller Supported Boundary-Scan
Instruction Opcodes” on page 517.
• Table 178, “Processor Integrated I/O TAP Controller Supported Boundary-Scan
Instruction Opcodes” on page 518.
14.3.1 Processor Core TAP Controller
The instruction register length is 8 bits, and the capture value is "00000001" binary.
14.3.2 Processor Un-Core TAP Controller
The instruction register length is 8 bits, and the capture value is "00000001" binary.
14.3.3 Processor Integrated I/O TAP Controller
The instruction register length is 8 bits, and the capture value is "00000001" binary.
Table 176. Processor Core TAP Controller Supported Boundary-Scan Instruction Opcodes
Opcode
(Hex)
Instruction Selected Test Data Register TDR Length
0x00h EXTEST Bypass 1
0x01h
SAMPLE/
PRELOAD (SAMPRE)
Bypass 1
0x02h IDCODE Device Identification 32
0x04h CLAMP Bypass 1
0x08h HIGHZ Bypass 1
0xFFh BYPASS Bypass 1
others Reserved
Table 177. Processor Un-Core TAP Controller Supported Boundary-Scan Instruction
Opcodes
Opcode
(binary)
Instruction Selected Test Data Register TDR Length
0x00h EXTEST Boundary-scan 569
0x01h
SAMPLE/
PRELOAD (SAMPRE)
Boundary-scan 134
0x01h
SAMPLE/
PRELOAD (SAMPRE)
Boundary-scan 569
0x02h IDCODE Device Identification 32
0x04h CLAMP Bypass 1
0x08h HIGHZ Bypass 1
0xFFh BYPASS Bypass 1
others Reserved