Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 515
Testability
14.0 Testability
The processor includes boundary-scan for board and system level testability.
14.1 Boundary-Scan
The processor is compatible with the IEEE 1149.1-2001 (Standard Test Access Port and
Boundary-Scan Architecture) specification. See the specification for functionality.
After applying voltage to the power pins, the following initialization sequence must be
completed prior to first TAP (Test Access Port) accesses that apply the boundary-scan
test patterns:
• The BCLK pins must be clocked.
• VCCPWRGOOD_1 pin must be held LOW for a minimum of 1us and then driven
HIGH prior to the first TAP access (the other power good pins, VTTPWRGOOD and
VCCPWRGOOD_0 must be asserted for correct TAP operation).
• The RSTIN# pin must be driven LOW (active) initially until after VCCPWRGOOD_1
is driven HIGH. RSTIN# may be held low or driven high during application of
boundary-scan patterns.
14.2 TAP Controller Operation and State Diagram
Figure 88 shows the state diagram for the TAP controller Finite State Machine. The TAP
controllers are asynchronously reset via the hardware TAP reset. Once reset is
deasserted, the TAP controllers sample the TMS pin at the rising edge of TCK pin, and
sequence through the states under the control of the TMS pin.
Holding the TMS pin high for five or more TCK cycles will take the TAP controllers to the
Test-Logic-Reset state regardless of what state they are in. It is recommended that
TMS be held high at the desassertion of reset to ensure deterministic operation of the
TAP controllers. The TDO pin is output-enabled only during Shift-DR or Shift-IR states.