Datasheet

Electrical Specifications
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 January 2010
512 Order Number: 323103-001
13.6.6 PECI Signal DC Specifications
The following table defines the parameters for PECI.
13.6.7 System Reference Clock Signal DC Specifications
The following table defines the parameters for System Reference Clock.
Table 170. PECI DC Electrical Limits
Symbol Definition and Conditions Min Max Units Notes
1
V
In
Input Voltage Range -0.150 V
TTD
+ 0.150 V
V
Hysteresis
Hysteresis 0.100 * V
TTD
V
V
N
Negative-edge threshold voltage 0.275 * V
TTD
0.500 * V
TTD
V2,6
V
P
Positive-edge threshold voltage 0.550 * V
TTD
0.725 * V
TTD
V2,6
R
Pullup
Pullup Resistance
(V
OH
= 0.75 * V
TTD
)
50 Ohms
I
Leak+
High impedance state leakage to
V
TTD
(V
leak
= V
OL
)
50 µA 3
I
Leak-
High impedance leakage to GND
(V
leak
= V
OH
)
25 µA 3
C
Bus
Bus capacitance per node 10 pF 4,5
V
Noise
Signal noise immunity above
300 MHz
0.100 * V
TTD
V
p-p
Notes:
1. V
TTD
supplies the PECI interface. PECI behavior does not affect V
TTD
min/max specifications.
2. It is expected that the PECI driver will take into account, the variance in the receiver input thresholds
and consequently, be able to drive its output within safe limits (-0.150 V to 0.275*V
TTD
for the low
level and 0.725*V
TTD
to V
TTD
+0.150 for the high level).
3. The leakage specification applies to powered devices on the PECI bus.
4. One node is counted for each client and one node for the system host. Extended trace lengths might
appear as additional nodes.
5. Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and
consequently limit the maximum bit rate at which the interface can operate.
6. See Figure 84 for further information.
Table 171. System Reference Clock DC Specifications
Symbol Parameter Min Max Unit Notes
1
V
Refclk_diff_ih
Differential Input High Voltage 0.150 V
V
Refclk_diff_il
Differential Input Low Voltage -0.150 V
V
cross
(abs)
Absolute
Crossing Point
0.250 0.550 V 2, 4
V
cross
(rel)
Relative
Crossing Point
0.250 +
0.5*(VH
avg
- 0.700)
0.550 +
0.5*(VH
avg
- 0.700)
V3,4,5
ΔV
cross
Range of
Crossing Points
0.140 V 6
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing Voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal
to the falling edge of BCLK1.
3. V
Havg
is the statistical average of the VH measured by the oscilloscope.
4. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
5. V
Havg
can be measured directly using “Vtop” on Agilent* and “High” on Tektronix oscilloscopes.
6. V
CROSS
is defined as the total variation of all crossing voltages as defined in Note 2.