Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
January 2010 Datasheet, Volume 1
Order Number: 323103-001 511
Electrical Specifications
13.6.5 SMBus Signal DC Specifications
The following tables define the parameters for SMBus.
Table 168. PCI Express Interface -- 2.5 and 5.0 GT/s Recevier DC Specifications
Symbol Parameter 2.5 GT/s 5.0 GT/s Units Comments
ZRX-DC
Receiver DC
common mode
impedance
40 (min)
60 (max)
40 (min)
60 (max)
Ohms
DC impedance limits are needed to
guarantee Receiver detect.
ZRX-DIFF-DC
DC differential
impedance
80 (min)
120 (max)
Not specified Ohms
For 5.0 GT/s covered under RL
RX-DIFF
parameter.
ZRX-HIGH-
IMP-DCPOS
DC Input CM Input
Impedance for V>0
during Reset or
power down
50 k (min) 50 k (min) Ohms
Rx DC CM impedance with the Rx
terminations not powered, measured
over the range 0 - 200 mV with respect
to ground.
ZRX-HIGH-
IMP-DCNEG
DC Input CM Input
Impedance for V<0
during Reset or
power down
1.0 k (min) 1.0 k (min) Ohms
Rx DC CM impedance with the Rx
terminations not powered, measured
over the range -150 - 0 mV with respect
to ground.
VRX-IDLE-
DET-DIFFp-p
Electrical Idle Detect
Threshold
65 (min)
175 (max)
65 (min)
175 (max)
mV
V
RX-IDLE-DET-DIFFp-p
= 2*|V
RX-D+ - VRXD-
|. Measured at the package pins of the
Receiver.
Table 169. SMBus Clock DC Electrical Limits
Symbol Parameter Min Typ Max Units Notes
1
V
IL
Input Low Voltage 0.64
*
V
TTA
V2,3
V
IH
Input High Voltage 0.76
*
V
TTA
2
V
OL
Output Low Voltage
V
TTA
* R
ON
/
(R
ON
+ R
SYS_TERM
)
V2,4
V
OH
Output High Voltage V
TTA
V2
R
ON
IO Buffer On Resistance 10 18 Ohms
I
LI
Input Leakage Current ± 200 μA
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V
TTA
referred to in these specifications refers to instantaneous V
TTA
.
3. Based on a test load of 50 Ohms to V
TTA.
4. R
SYS_TERM
is the termination on the system and is not controlled by the Intel
®
Xeon
®
processor
C5500/C3500 series.