Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
January 2010 Datasheet, Volume 1
Order Number: 323103-001 509
Electrical Specifications
R
ON
DDR3 Data Buffer On
Resistance
21 31 Ohms 5
Data ODT
On-Die Termination for
Data Signals
45
90
55
110
Ohms 7
ParErr ODT
On-Die Termination for
Parity Error bits
60 80 Ohms
I
LI
Input Leakage Current ± 500 mA
DDR_COMP0 COMP Resistance 99 100 101 Ohms 8
DDR_COMP1 COMP Resistance 24.65 24.9 25.15 Ohms 8
DDR_COMP2 COMP Resistance 128.7 130 131.3 Ohms 8
Table 166. DDR3 Signal Group DC Specifications (Sheet 2 of 2)
Symbol Parameter Min Typ Max Units Notes
1
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
OH
may experience excursions above V
DDQ
. However, input signal drivers must comply with the
signal quality specifications.
5. This is the pull down driver resistance. See the processor signal integrity models for I/V characteristics.
6. R
VTT_TERM
is the termination on the DIMM and not controlled by the Intel
®
Xeon
®
processor C5500/C3500
series. See the applicable DIMM datasheet.
7. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.
8. COMP resistance must be provided on the system board with 1% resistors. See the Picket Post: Intel
®
Xeon
®
Processor C5500/C3500 Series with the Intel
®
3420 Chipset Platform Design Guide (PDG) for
implementation details. DDR_COMP[2:0] resistors are to Vss.