Datasheet
Electrical Specifications
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 January 2010
508 Order Number: 323103-001
13.6.2 Die Voltage Validation
Core voltage (V
CC
) overshoot events at the processor must meet the specifications in
Table 164 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot
events that are < 10 ns in duration may be ignored. These measurements of processor
die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.
13.6.3 DDR3 Signal DC Specifications
The following table defines the parameters for DDR3.
Table 165. ICC Max and ICC TDP by SKU
SKU ICC
MAX
ICC
TDC
ECC5549 100 70
ECC5509 75 70
ECC3539 55 50
LC5528 70 50
EC5539 42 40
LC5518 54 39
P1053 13 12
LC3528 24 20
LC3518 11 10
Table 166. DDR3 Signal Group DC Specifications (Sheet 1 of 2)
Symbol Parameter Min Typ Max Units Notes
1
V
IL
Input Low Voltage 0.43*V
DDQ
V2,
V
IH
Input High Voltage 0.57*V
DDQ
V3, 4
V
OL
Output Low Voltage
(V
DDQ
/ 2)* (R
ON
/
(R
ON
+R
VTT_TERM
))
V6
V
OH
Output High Voltage
V
DDQ
- ((V
DDQ
/ 2)*
(R
ON
/(R
ON
+R
VTT_TERM
))
V4,6
R
ON
DDR3 Clock Buffer On
Resistance
21 31 Ohms 5
R
ON
DDR3 Command Buffer
On Resistance
16 24 Ohms 5
R
ON
DDR3 Reset Buffer On
Resistance
25 75 Ohms 5
R
ON
DDR3 Control Buffer
On Resistance
21 31 Ohms 5
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
OH
may experience excursions above V
DDQ
. However, input signal drivers must comply with the
signal quality specifications.
5. This is the pull down driver resistance. See the processor signal integrity models for I/V characteristics.
6. R
VTT_TERM
is the termination on the DIMM and not controlled by the Intel
®
Xeon
®
processor C5500/C3500
series. See the applicable DIMM datasheet.
7. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.
8. COMP resistance must be provided on the system board with 1% resistors. See the Picket Post: Intel
®
Xeon
®
Processor C5500/C3500 Series with the Intel
®
3420 Chipset Platform Design Guide (PDG) for
implementation details. DDR_COMP[2:0] resistors are to Vss.