Datasheet

Electrical Specifications
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 January 2010
502 Order Number: 323103-001
Table 162. Voltage and Current Specifications (Sheet 1 of 3)
Symbol Parameter
Voltage
Plane
Min Typ Max Unit Notes
1
VID V
CC
VID Range - 0.750 1.350 V 2,3
V
CC
Core Voltage
(Launch - FMB)
V
CC
See Table 163 and Figure 86 V
3,4,6,7,
11
V
VID_STEP
VID step size during a
transition
- ± 6.250 mV 9
V
CCPLL
PLL Voltage
(DC + AC specification)
V
CCPLL
0.95*V
CCPLL
(Typ)
1.800
1.05*V
CCPLL
(Typ)
V10
V
DDQ
I/O Voltage for DDR3 (DC +
AC specification)
V
DDQ
0.95*V
DDQ
(Typ)
1.500
1.05*V
DDQ
(Typ)
V10
VTT_VID V
TT
VID Range - 1.045 1.220 V 2,3
V
TT
Uncore Voltage
(Launch - FMB)
V
TT
See Table 173 V 3,5,8,11
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are
based on pre-silicon characterization and will be updated as further data becomes available.
2. Individual processor VID and/or VTT_VID values may be calibrated during manufacturing such that
two devices at the same speed may have different settings.
3. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required.
4. The V
CC
voltage specification requirements are measured across vias on the platform for VCCSENSE
and VSSSENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum
probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe
should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
5. The V
TT
voltage specification requirements are measured across platform vias for VTTD_SENSE and
VSS_SENSE_VTTD lands close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum
probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe
should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
6. See Table 163 and corresponding Figure 86. The processor should not be subjected to any static V
CC
level that exceeds the V
CC_MAX
associated with any particular current. Failure to adhere to this
specification can shorten processor lifetime.
7. Minimum V
CC
and maximum I
CC
are specified at the maximum processor case temperature (T
CASE
)
shown in the Intel
®
Xeon
®
Processor C5500/C3500 Series Thermal / Mechanical Design Guide.
I
CC_MAX
is specified at the relative V
CC_MAX
point on the V
CC
load line. The processor is capable of
drawing I
CC_MAX
for up to 10 ms.
8. See Table 173. Do not subject processor to any static V
TT
level exceeding V
TT_MAX
associated with any
particular current. Failure to adhere to this specification can shorten processor lifetime.
9. This specification represents the V
CC
reduction due to each VID transition. See Section 13.1.10.3. .
10. Baseboard bandwidth is limited to 20 MHz.
11. FMB is the flexible motherboard guidelines. See Section 13.4 for FMB details.