Datasheet

Interfaces
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 February 2010
50 Order Number: 323103-001
2.1.7.1 Enabling SMI/NMI for Memory Corrected Errors
The MC_SMI_SPARE_CNTRL register has enables for SMI and NMI interrupts. Only one
should be set. Whichever type of interrupt is enabled will be triggered if:
• a DIMM error counter exceeds the threshold,
• redundancy is lost on a mirrored configuration, or
• a sparing operation completes.
This register is set by hardware once operation is complete. Bit is cleared by hardware
when a new operation is enabled. An SMI is generated when this bit is set due to a
sparing copy completion event.
Such an interrupt, once enabled by software, will be signaled only to the local
processor package where these events were detected. Therefore, the SMI/NMI
interrupt handler must be aware of the fact that the other processor package, if
present, did not receive the signalling of such SMI/NMI event.
2.1.7.2 Per DIMM Error Counters
There is one correctable ECC error counter for each DIMM that can be connected to the
Integrated Memory Controller. There are six MC_COR_ECC_CNT_X registers, each of
which holds a 15-bit counter and overflow bits for two DIMMs. The
Figure 9. Error Signaling Logic