Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 5
2.3.5 Addressing ............................................................................................95
2.3.6 SMBus Initiated Southbound Configuration Cycles.......................................97
2.3.7 SMBus Error Handling............................................................................. 97
2.3.8 SMBus Interface Reset............................................................................97
2.3.9 Configuration and Memory Read Protocol...................................................98
2.3.9.1 SMBus Configuration and Memory Block-Size Reads.....................99
2.3.9.2 SMBus Configuration and Memory Word-Size Reads................... 100
2.3.9.3 SMBus Configuration and Memory Byte Reads........................... 101
2.3.9.4 Configuration and Memory Write Protocol................................. 103
2.3.9.5 SMBus Configuration and Memory Block Writes......................... 103
2.3.9.6 SMBus Configuration and Memory Word Writes ......................... 104
2.3.9.7 SMBus Configuration and Memory Byte Writes .......................... 104
2.4 Intel
®
QuickPath Interconnect (Intel
®
QPI) ........................................................ 105
2.4.1 Processor’s Intel
®
QuickPath Interconnect Platform Overview..................... 105
2.4.2 Physical Layer Implementation............................................................... 107
2.4.2.1 Processor’s Intel
®
QuickPath Interconnect Physical Layer
Attributes .............................................................................. 107
2.4.3 Processor’s Intel
®
QuickPath Interconnect Link Speed Configuration ........... 107
2.4.3.1 Detect Intel
®
QuickPath Interconnect Speeds Supported by the
Processors ............................................................................. 107
2.4.4 Intel
®
QuickPath Interconnect Probing Considerations............................... 108
2.4.5 Link Layer........................................................................................... 108
2.4.5.1 Link Layer Attributes ............................................................. 108
2.4.6 Routing Layer ...................................................................................... 108
2.4.6.1 Routing Layer Attributes ........................................................ 108
2.4.7 Intel
®
QuickPath Interconnect Address Decoding...................................... 109
2.4.8 Transport Layer ................................................................................... 109
2.4.9 Protocol Layer...................................................................................... 109
2.4.9.1 Protocol Layer Attributes........................................................ 109
2.4.9.2 Intel
®
QuickPath Interconnect Coherent Protocol Attributes........ 110
2.4.9.3 Intel
®
QuickPath Interconnect Non-Coherent Protocol Attributes . 110
2.4.9.4 Interrupt Handling ................................................................ 110
2.4.9.5 Fault Handling ...................................................................... 111
2.4.9.6 Reset/Initialization ................................................................ 111
2.4.9.7 Other Attributes.................................................................... 111
2.5 IIO Intel
®
QPI Coherent Interface and Address Decode ........................................ 111
2.5.1 Introduction ........................................................................................ 111
2.5.2 Link Layer........................................................................................... 112
2.5.2.1 Link Error Protection.............................................................. 112
2.5.2.2 Message Class...................................................................... 112
2.5.2.3 Link-Level Credit Return Policy................................................ 112
2.5.2.4 Ordering.............................................................................. 112
2.5.3 Protocol Layer...................................................................................... 113
2.5.4 Snooping Modes................................................................................... 113
2.5.5 IIO Source Address Decoder (SAD)......................................................... 113
2.5.5.1 NodeID Generation................................................................ 114
2.5.5.2 Memory Decoder................................................................... 114
2.5.5.3 I/O Decoder......................................................................... 114
2.5.6 Special Response Status........................................................................ 115
2.5.7 Illegal Completion/Response/Request...................................................... 115
2.5.8 Inbound Coherent ................................................................................ 116
2.5.9 Inbound Non-Coherent.......................................................................... 116
2.5.9.1 Peer-to-Peer Tunneling .......................................................... 116
2.5.10 Profile Support..................................................................................... 116
2.5.11 Write Cache......................................................................................... 117
2.5.11.1 Write Cache Depth................................................................ 117