Datasheet
Intel
®
Xeon
®
Processor C5500/C3500 Series
January 2010 Datasheet, Volume 1
Order Number: 323103-001 499
Electrical Specifications
Signals that include on-die termination (ODT) are listed in Table 160.
Notes:
1. Unless otherwise specified, signals have ODT in the package with a 50 Ohm pull-down to V
SS
.
2. Unless otherwise specified, all DDR3 signals are terminated to V
DDQ
/2.
3. DDRA_PAR_ERR#[2:0], DDRB_PAR_ERR#[2:0], and DDRC_PAR_ERR#[2:0] are terminated to V
DDQ.
4. TCK does not include ODT, this signal is weakly pulled-down via a 1-5 kOhm resistor to V
SS
.
5. TDI, TMS, TRST# do not include ODT, these signals are weakly pulled-up via ~ 10 kOhm resistor to V
TT
.
6. BPM[7:0]# and PREQ# signals have ODT in package with 35 Ohm pull-ups to V
TT.
7. PECI_ID# has ODT in package with a 1-5 kOhm pull-up to V
TT
.
8. VCCPWRGOOD, VTTPWRGOOD, and DDR_DRAMPWROK have ODT in package with a 5-20 kOhm pull-
down to V
SS
.
9. DP_SYNCRST, EXTSYSTRG, PMSYNC, and TDI_M have a 50 ohm ODT to Vtt.
Power / Ground Analog V
SS
Analog Input ISENSE
Analog VCCSENSE
Analog VSSSENSE
Analog VSS_SENSE_VTTD
Analog VTTD_SENSE
Single ended
CMOS (Push-Pull) Output (CMOS Input
during power up for POC straps)
VID[7:6],
VID[5:3]/CSC[2:0],
VID[2:0]/MSID[2:0]
Single ended CMOS (Push-Pull) Output VTT_VID[4:2]
No Connect & Reserved Signals
NC_x
RSV_x
1. See Section 6.0, “System Address Map” for signal definitions.
2. DDR3A refers to DDR3 Channel A, DDR3B refers to ChannelB, and DDR3C refers to Channel C.
Table 159. Signal Groups (Sheet 5 of 5)
Signal Group Buffer Type Signals
1
Table 160. Signals With On-Die Termination (ODT)
Intel
®
QuickPath Interface Signal Group
1
QPI_RX_DP[19:0], QPI_RX_DN[19:0], QPI_TX_DP[19:0], QPI_TX_DN[19:0], QPI_CLKRX_DN,
QPI_CLKRX_DP, QPI_CLKTX_DN, QPI_CLKTX_DP
PCI Express Signals
PE_RX_DN[15:0], PE_RX_DP[15:0], PE_TX_DN[15:0], PE_TX_DP[15:0]
DDR3 Signal Group
2
DDRA_DQ[63:0], DDRB_DQ[63:0], DDDRC_DQ[63:0], DDRA_DQS_N[17:0], DDRA_DQS_P[17:0],
DDRB_DQS_N[17:0], DDRB_DQS_P[17:0], DDRC_DQS_N[17:0], DDRC_DQS_P[17:0], DDRA_ECC[7:0],
DDRB_ECC[7:0], DDRC_ECC[7:0], DDRA_PAR_ERR#[2:0], DDRB_PAR_ERR#[2:0], DDRC_PAR_ERR#[2:0]
3
Reset and Miscellanous Signal Group and Thermal Signal Group
1
BPM#[7:0]
6
, PECI_ID#
7
, PREQ#
6
, DP_SYNCRST#
9
, EXTSYSTRG
9
, PMSYNC
9,
DDR_ADR
9
Test Access Port (TAP) Signal Group
TCK
4
, TDI
5
, TMS
5
, TRST#
5
, TDI_M
9
Power/Other Signal Group
8
VCCPWRGOOD, VTTPWRGOOD, DDR_DRAMPWROK