Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
January 2010 Datasheet, Volume 1
Order Number: 323103-001 497
Electrical Specifications
Differential CMOS Input/Output DDRB_DQS_DN[17:0]
Differential CMOS Input/Output DDRB_DQS_DP[17:0]
Single ended CMOS Input/Output DDRB_ECC[7:0]
Single ended CMOS Output DDRB_MA_[15:0]
Single ended CMOS Output DDRB_MA_PAR
Single ended CMOS Output DDRB_ODT[3:0]
Single ended Asynchronous Input DDRB_PAR_ERR[2:0]
Single ended CMOS Output DDRB_RAS#
Single ended Asynchronous Output DDRB_Reset#
Single ended CMOS Output DDRB_WE#
DDR Channel C Signals
2
Single ended CMOS Output DDRC_BA[2:0]
Single ended CMOS Output DDRC_CAS#
Single ended CMOS Output DDRC_CKE[3:0]
Differential Output DDRC_CLK_DN[3:0]
Differential Output DDRC_CLK_DP[3:0]
Single ended CMOS Output DDRC_CS[7:0]#
Single ended CMOS Input/Output DDRC_DQ[63:0]
Differential CMOS Input/Output DDRC_DQS_DN[17:0]
Differential CMOS Input/Output DDRC_DQS_DP[17:0]
Single ended CMOS Input/Output DDRC_ECC[7:0]
Single ended CMOS Output DDRC_MA_[15:0]
Single ended CMOS Output DDRC_MA_PAR
Single ended CMOS Output DDRC_ODT[3:0]
Single ended Asynchronous Input DDRC_PAR_ERR[2:0]
Single ended CMOS Output DDRC_RAS#
Single ended Asynchronous Output DDRC_Reset#
Single ended CMOS Output DDRC_WE#
DDR Compensation Signals
2
Single ended Analog Input DDR_COMP[2:0]
System Management Bus (SMBus)
Single ended SMB Input/Output SMB_CLK
Single ended SMB Input/Output SMB_DATA
Platform Environmental Control Interface (PECI)
Single ended Asynchronous Input/Output PECI
Reset and Miscellaneous Signals
Single Ended Asynchronous Input RSTIN#
Single Ended CMOS Input/Output DP_SYNCRST#
Single Ended Analog COMP0
Table 159. Signal Groups (Sheet 3 of 5)
Signal Group Buffer Type Signals
1