Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
January 2010 Datasheet, Volume 1
Order Number: 323103-001 495
Electrical Specifications
13.1.11 Reserved or Unused Signals
Unless otherwise specified, all Reserved (RSVD) signals should be left as No Connect.
Connection of these signals to V
CC
, V
TTA
, V
TTD
, V
DDQ
, V
SS
, or any other signal (including
each other) can result in component malfunction or incompatibility with future
processor.
For reliable operation, connect unused input signals to an appropriate signal level.
Unused Intel
®
QuickPath Interconnect input and output pins can be left floating.
Unused active high inputs should be connected through a resistor to ground (V
SS
).
Unused outputs can be left unconnected; however, this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, including a resistor will also allow for system testability.
Resistor values should be within ± 20% of the impedance of the baseboard trace,
unless otherwise noted in the appropriate platform design guidelines.
TAP signals do not include on-die termination, however they may include resistors on
package (see Section 13.1.9 for details). Inputs and utilized outputs must be
terminated on the board. Unused outputs may be terminated on the board or left
unconnected. Leaving unused outputs unterminated may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. Signal
termination requirements are detailed in the Picket Post: Intel
®
Xeon
®
Processor
C5500/C3500 Series with the Intel
®
3420 Chipset Platform Design Guide (PDG).
13.2 Signal Group Summary
Signals are combined in Table 159 by buffer type and characteristics. “Buffer Type”
denotes the applicable signaling technology and specifications.
Table 158. V
TT
Voltage Identification Definition
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VR 11.0
Voltage
V
TT_TYP
(Voltage + Offset)
010
0 0 0 1 0 1.200V 1.220V
010
0 0 1 1 0 1.175V 1.195V
010
0 1 0 1 0 1.150V 1.170V
010
0 1 1 1 0 1.125V 1.145V
010
1 0 0 1 0 1.100V 1.120V
010
1 0 1 1 0 1.075V 1.095V
010
1 1 0 1 0 1.050V 1.070V
010
1 1 1 1 0 1.025V 1.045V
Table 159. Signal Groups (Sheet 1 of 5)
Signal Group Buffer Type Signals
1
PCI Express Signals
Differential PCI Express Input PE_RX_DN[15:0], PE_RX_DP[15:0]
Differential PCI Express Output PE_TX_DN[15:0], PE_TX_DP[15:0]
Single ended Analog Input
PE_ICOMPO, PE_ICOMPI, PE_RCOMPO,
PE_RBIAS
Differential PCI Express Input PE_CLK_D[P/N]