Datasheet

Electrical Specifications
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 January 2010
494 Order Number: 323103-001
13.1.10.3.2 Power-On Configuration (POC)
Several configuration options can be configured by hardware. Power-on configuration
(POC) functionality is either MUx’ed onto VID signals (see Section 13.1.10.3) or
sampled on the active-to-inactive transition of RSTIN#. For specifics on these options,
See Table 158.
Requests to execute Built-In Self Test (BIST) are not selected by hardware, but rather
passed across the Intel
®
QuickPath Interconnect link during initialization.
Figure 85 outlines the timing associated with VID[2:0]/MSID[2:0] sampling. After
OUTEN is asserted, the VID[7:0] CMOS drivers (typically 50 Ohms up/down
impedance) over-ride the POC pull-up/down resistors located on the baseboard and
drive the necessary VID pattern.
13.1.10.4 Processor V
TT
Voltage Identification (VTT_VID) Signals
The VTT Voltage Identification (VTT_VID) specification is defined by the Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design
Guidelines, Revision 1.5. The voltage set by the VTT_VID signals is the typical
reference voltage regulator (VR) output to be delivered to the processor V
TTA
and V
TTD
lands. It is expected that one regulator will supply all V
TTA
and V
TTD
lands. VTT_VID
signals are CMOS push/pull outputs. See Table 172 for the DC specifications for these
signals.
Individual processor VTT_VID values may be calibrated during manufacturing such that
two processor units with the same core frequency may have different default VTT_VID
settings.
The processor
utilizes three voltage identification signals to support automatic selection
of power supply voltages. These correspond to VTT_VID[4:2] as defined in the Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.1 Design
Guidelines, Revision 1.5. The V
TT
voltage level delivered to the processor lands must
also encompass a 20 mV offset (See Table 158; V
TT_TYP
) above the voltage level
corresponding to the state of the VTT_VID[7:0] signals (See Table 158; VR 11.0
Voltage).
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
Note: For available SKUs, see Table 1, “Available SKUs”. For voltage and current
specifications, see Table 162.
Figure 85. MSID Timing Requirement
VTTPWRGOOD
VID[7:0]
POC
MSID
Min Setup (1us)
10 us
Min Hold (50ns)