Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
January 2010 Datasheet, Volume 1
Order Number: 323103-001 493
Electrical Specifications
Note:
• The expected voltage range is 1.35-0.75v.
• When the “11111111” VID pattern is observed, or when the SKTOCC# pin is high,
the voltage regulator output should be disabled.
• Shading denotes the expected VID range of the processor.
• The VID range includes VID transitions that may be initiated by thermal events,
Extended HALT state transitions (see Section 8.2, “Processor Core Power
Management”), higher C-States (see Section 8.2.4, “Core C-States”) or Enhanced
Intel SpeedStep
®
Technology transitions (see Section 8.2.1, “Enhanced Intel
SpeedStep® Technology”). The Extended HALT state must be enabled for the
processor to remain within its specifications.
• Once the VRM/EVRD is operating after power-up, if either the Output Enable signal
is de-asserted or a specific VID off code is received, the VRM/EVRD must turn off its
output (the output should go to high impedance) within 500 ms and latch off until
power is cycled. See the Voltage Regulator Module (VRM) and Enterprise Voltage
Regulator-Down (EVRD) 11.1 Design Guidelines, Revision 1.5.
13.1.10.3.1 Power-On Configuration (POC) Logic
VID[7:0] signals also serve a second function. During power-up, Power-On
Configuration POC[7:0] functionality is multiplexed onto these signals via 1-5 kOhms
pull-up or pull down resistors located on the board. These values provide voltage
regulator keying (VID[7]), inform the processor of the platforms power delivery
capabilities (MSID[2:0]), and program the gain applied to the ISENSE input
(CSC[2:0]). Table 157 maps VID signals to the corresponding POC functionality.
Some POC signals include specific timing requirements. See the following section for
details.
Table 157. Power-On Configuration (POC[7:0]) Decode
Function Bits POC Settings Description
VR_Key VID[7] 0b for VR11.1
Electronic safety key
distinguishing VR11.1
Spare VID[6] 0b (default) Reserved for future use
CSC[2:0] VID[5:3]
000
001
010
011
100
101
110
111
Feature Disabled
ICC_MAX ≤ 40A
40A ≤ ICC_MAX ≤ 60A
60A ≤ ICC_MAX ≤ 80A
80A ≤ ICC_MAX ≤ 100A
100A ≤ ICC_MAX ≤ 120A
120A ≤ ICC_MAX ≤ 140A
140A ≤ ICC_MAX ≤ 180A
Current Sensor Configuration
(CSC) programs the gain
applied to the ISENSE A/D
output. ISENSE data is then
used to dynamically calculate
current and power.
See the Voltage Regulator
Module (VRM) and Enterprise
Voltage Regulator-Down
(EVRD) 11.1 Design Guidelines,
Revision 1.5 for further details
on the IMON signal.
MSID[2:0] VID[2:0]
000
001
010
011
100
101
110
111
Undefined
Undefined
Undefined
60W TDP / 80A ICC_MAX
80W TDP / 100A ICC_MAX
95W TDP / 120A ICC_MAX
130W TDP / 150A ICC_MAX
Undefined
MSID[2:0] signals are provided
to indicate the Market Segment
for the processor and may be
used for future processor
compatibility or keying. See
Figure 85 for platform timing
requirements of the MSID[2:0]
signals.