Datasheet

Intel
®
Xeon
®
Processor C5500/C3500 Series
February 2010 Datasheet, Volume 1
Order Number: 323103-001 49
Interfaces
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
2.1.5.2 Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
2.1.5.3 Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6 DDR3 On-Die Termination
On-Die Termination (ODT) allows a DRAM device to turn on/off internal termination
resistance for each DQ, DQS/DQS#, and DM signal via the ODT control pin.
ODT provides improved signal integrity of the memory channel by allowing the DRAM
controller to independently turn on or off the termination resistance for any or all DRAM
devices themselves instead of on the motherboard.
The IMC drives out the required ODT signals, based on the memory configuration and
which rank is being written to or read from, to the DRAM devices on a targeted DIMM
module rank to enable or disable their termination resistance.
2.1.7 Memory Error Signaling
Uncorrected memory errors are reported via Machine Check Architecture. An
uncorrected memory error is logged in Machine Check Bank8 registers, causes a
Machine Check Exception (MCE) signaled to all processor packages, and asserts
CATERR#, which can be optionally used by a platform to trigger an SMI event.
Corrected memory errors are reported via two independent mechanisms: CMCI
signaling based on Machine Check Architecture and Machine Check Bank8 registers,
and SMI/NMI signaling based on CSR registers located in the Integrated Memory
Controller.
CMCI and Machine Check Architecture based memory error signaling is intended to be
handled by the OS. This subsection covers the SMI/NMI signaling of corrected memory
errors based on CSR registers.
Figure 9 depicts this logic.