Datasheet

Electrical Specifications
Intel
®
Xeon
®
Processor C5500/C3500 Series
Datasheet, Volume 1 January 2010
486 Order Number: 323103-001
13.1.6 Clock Signals
The processor core, processor uncore, Intel
®
QuickPath Interconnect link, and DDR3
memory interface frequencies are generated from BCLK_DP and BCLK_DN signals.
There is no direct link between core frequency and Intel
®
QuickPath Interconnect link
frequency (e.g., no core frequency to Intel
®
QuickPath Interconnect multiplier). The
processor maximum core frequency, Intel
®
QuickPath Interconnect link frequency and
DDR3 memory frequency are set during manufacturing. It is possible to override the
processor core frequency setting using software. This permits operation at lower core
frequencies than the factory set maximum core frequency.
The processor core frequency is configured during reset by using values stored within
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured via the IA32_PERF_CTL MSR (MSR 199h); Bits
[15:0].
Clock multiplying within the processor is provided by the internal phase locked loop
(PLL), which requires a constant frequency BCLK_DP, BCLK_DN input, with exceptions
for spread spectrum clocking. DC specifications for the BCLK_DP, BCLK_DN inputs are
provided in Table 171. These specifications must be met while also meeting the
associated signal quality specifications.
Details regarding BCLK_DP, BCLK_DN driver specifications are provided in the CK410B
Clock Synthesizer/Driver Design Guidelines.
13.1.7 Reset and Miscellaneous
The Intel
®
Xeon
®
processor C5500/C3500 series includes signals that provide a variety
of functions. Details are in Table 159 and in the applicable platform design guide.
See Table 172 and for DC specifications.
13.1.8 Thermal
Intel
®
Xeon
®
processor C5500/C3500 series includes signals that support the thermal
management feature. These thermal signals serve as indication and protection when
the processor reaches a potential overheating condition. Details are in Table 159.
See Table 173 for DC specifications.
13.1.9 Test Access Port (TAP) Signals
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
connect to the rest of the chain unless one of the other components is capable of
accepting an input of the appropriate voltage. Similar considerations must be made for
TDI, TDI_M, and TDO_M, TCLK, TDO, TMS, and TRST#. Two copies of each signal may
be required with each driving a different voltage level.
Processor TAP signal DC specifications are in Table 172.
13.1.10 Power / Other Signals
Processors also include various other signals including power/ground, sense points, and
analog inputs. Details are in Table 159 and in the applicable platform design guide.